| /external/llvm/lib/Target/ARM/ |
| ARMInstrInfo.cpp | 126 MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL,
130 MIB.addImm(0);
131 AddDefaultPred(MIB);
|
| Thumb2InstrInfo.cpp | 157 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
158 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
159 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
160 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
161 AddDefaultPred(MIB);
198 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
201 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
202 AddDefaultPred(MIB);
[all...] |
| Thumb1RegisterInfo.cpp | 130 MachineInstrBuilder MIB =
133 MIB = AddDefaultT1CC(MIB);
135 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
137 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
138 AddDefaultPred(MIB);
242 const MachineInstrBuilder MIB =
245 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
261 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
263 MIB = AddDefaultT1CC(MIB)
[all...] |
| MLxExpansionPass.cpp | 292 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg)
296 MIB.addImm(LaneImm);
297 MIB.addImm(Pred).addReg(PredReg);
299 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2)
304 MIB.addReg(TmpReg, getKillRegState(true))
307 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
309 MIB.addImm(Pred).addReg(PredReg);
|
| Thumb1FrameLowering.cpp | 320 MachineInstrBuilder MIB =
323 AddDefaultPred(MIB);
324 MIB.copyImplicitOps(&*MBBI);
344 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
345 AddDefaultPred(MIB);
363 MIB.addReg(Reg, getKillRegState(isKill));
365 MIB.setMIFlags(MachineInstr::FrameSetup);
383 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
384 AddDefaultPred(MIB);
394 (*MIB).setDesc(TII.get(ARM::tPOP_RET))
[all...] |
| Thumb2ITBlockPass.cpp | 181 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
189 MachineBasicBlock::iterator InsertPos = MIB;
232 MIB.addImm(Mask);
|
| ARMBaseRegisterInfo.cpp | 580 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
584 AddDefaultCC(MIB);
|
| ARMExpandPseudoInsts.cpp | 383 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
400 MIB.addOperand(MI.getOperand(OpIdx++));
403 MIB.addOperand(MI.getOperand(OpIdx++));
404 MIB.addOperand(MI.getOperand(OpIdx++));
407 MIB.addOperand(MI.getOperand(OpIdx++));
417 MIB.addOperand(MI.getOperand(OpIdx++))
[all...] |
| ARMFrameLowering.cpp | 224 MachineInstrBuilder MIB =
228 AddDefaultCC(AddDefaultPred(MIB));
449 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
451 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
455 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
460 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
630 MachineInstrBuilder MIB =
634 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
636 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
641 AddDefaultPred(MIB);
[all...] |
| Thumb2SizeReduction.cpp | 496 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc));
498 MIB.addOperand(MI->getOperand(0));
499 MIB.addOperand(MI->getOperand(1));
502 MIB.addImm(OffsetImm / Scale);
507 MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
512 MIB.addOperand(MI->getOperand(OpNum));
515 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
518 MIB.setMIFlags(MI->getFlags());
520 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
556 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc()
[all...] |
| ARMLoadStoreOptimizer.cpp | 349 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))
353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
358 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine);
777 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
784 MIB.addOperand(MI->getOperand(OpNum));
787 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 100 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
104 MIB.addReg(Cond[i].getReg());
106 MIB.addImm(Cond[i].getImm());
110 MIB.addMBB(TBB);
280 MachineInstrBuilder MIB;
281 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
284 MIB.addOperand(I->getOperand(J));
286 MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end());
287 return MIB;
|
| Mips16InstrInfo.cpp | 91 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
94 MIB.addReg(DestReg, RegState::Define);
97 MIB.addReg(SrcReg, getKillRegState(KillSrc));
|
| MipsLongBranch.cpp | 225 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
235 MIB.addReg(MO.getReg());
238 MIB.addMBB(MBBOpnd);
|
| MipsSEInstrInfo.cpp | 165 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
168 MIB.addReg(DestReg, RegState::Define);
171 MIB.addReg(SrcReg, getKillRegState(KillSrc));
174 MIB.addReg(ZeroReg);
497 MachineInstrBuilder MIB = genInstrWithNewOpc(OpcS, I);
498 MIB->getOperand(0).setReg(LoReg);
502 MIB = genInstrWithNewOpc(OpcS, I);
503 MIB->getOperand(0).setReg(HiReg);
504 fixDisp(MIB->getOperand(2));
|
| /external/llvm/lib/CodeGen/ |
| MachineInstrBundle.cpp | 110 MachineInstrBuilder MIB = BuildMI(*MBB.getParent(), FirstMI->getDebugLoc(),
112 Bundle.prepend(MIB);
191 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
200 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 182 MachineInstrBuilder MIB =
185 MIB->copyImplicitOps(*MBB.getParent(), &*MBBI);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZFrameLowering.cpp | 106 // Add GPR64 to the save instruction being built by MIB, which is in basic
110 static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB,
117 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive));
176 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
179 addSavedGPR(MBB, MIB, TM, LowGPR, false);
180 addSavedGPR(MBB, MIB, TM, HighGPR, false);
183 MIB.addReg(SystemZ::R15D).addImm(StartOffset);
190 addSavedGPR(MBB, MIB, TM, Reg, true);
196 addSavedGPR(MBB, MIB, TM, SystemZ::ArgGPRs[I], true);
246 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG))
[all...] |
| SystemZInstrInfo.cpp | 489 MachineInstrBuilder MIB =
493 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
496 MIB.addOperand(MI->getOperand(I));
497 return finishConvertToThreeAddress(MI, MIB, LV);
524 MachineInstrBuilder MIB =
529 return finishConvertToThreeAddress(MI, MIB, LV);
615 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(MemOpcode));
617 MIB.addOperand(MI->getOperand(I));
618 MIB.addFrameIndex(FrameIndex).addImm(Offset);
620 MIB.addReg(0)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 226 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
228 MIB->addOperand(MBBI->getOperand(i)); // copy any variadic operands
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 214 MachineInstrBuilder MIB;
216 MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_Bimm));
218 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
222 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
229 MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_BRx));
230 MIB.addReg(JumpTarget.getReg(), RegState::Kill);
236 MIB->addOperand(MBBI->getOperand(i));
|
| AArch64InstrInfo.cpp | 301 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
303 MIB.addOperand(Cond[i]);
304 MIB.addMBB(TBB);
308 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
310 MIB.addOperand(Cond[i]);
311 MIB.addMBB(TBB);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 418 MachineInstrBuilder MIB =
421 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 841 MachineInstrBuilder MIB =
844 MIB.addReg(RetRegs[i], RegState::Implicit);
[all...] |
| X86InstrInfo.cpp | [all...] |
