| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 258 MCOperand NewReg;
263 NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
265 NewMI.addOperand(NewReg);
[all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| ExprEngineCXX.cpp | 386 const MemRegion *NewReg = symVal.castAs<loc::MemRegionVal>().getRegion();
389 getStoreManager().GetElementZeroRegion(NewReg, ObjTy);
|
| /external/llvm/lib/CodeGen/ |
| CriticalAntiDepBreaker.cpp | 303 // be replaced by NewReg. Return true if any of their parent instructions may
308 // the two-address instruction also defines NewReg, as may happen with
312 // both NewReg and AntiDepReg covers it.
316 unsigned NewReg)
322 // operands, in case they may be assigned to NewReg. In this case antidep
327 // Handle cases in which this instructions defines NewReg.
332 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg))
336 CheckOper.getReg() != NewReg)
339 // Don't allow the instruction to define NewReg and AntiDepReg.
345 // NewReg
[all...] |
| MachineCSE.cpp | 522 unsigned NewReg = CSMI->getOperand(i).getReg();
528 if (OldReg == NewReg) {
534 TargetRegisterInfo::isVirtualRegister(NewReg) &&
537 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
546 if (!MRI->constrainRegClass(NewReg, OldRC)) {
552 CSEPairs.push_back(std::make_pair(OldReg, NewReg));
|
| StrongPHIElimination.cpp | 139 // Merges the live interval of Reg into NewReg and renames Reg to NewReg
140 // everywhere that Reg appears. Requires Reg and NewReg to have non-
142 void MergeLIsAndRename(unsigned Reg, unsigned NewReg);
310 unsigned NewReg = RegRenamingMap[SrcColor];
311 if (!NewReg) {
312 NewReg = SrcReg;
315 MergeLIsAndRename(SrcReg, NewReg);
319 MergeLIsAndRename(DestReg, NewReg);
323 MergeLIsAndRename(SrcReg, NewReg);
[all...] |
| TailDuplication.cpp | 84 void AddSSAUpdateEntry(unsigned OrigReg, unsigned NewReg,
369 void TailDuplicatePass::AddSSAUpdateEntry(unsigned OrigReg, unsigned NewReg,
373 LI->second.push_back(std::make_pair(BB, NewReg));
376 Vals.push_back(std::make_pair(BB, NewReg));
432 unsigned NewReg = MRI->createVirtualRegister(RC);
433 MO.setReg(NewReg);
434 LocalVRMap.insert(std::make_pair(Reg, NewReg));
436 AddSSAUpdateEntry(Reg, NewReg, PredBB);
[all...] |
| TwoAddressInstructionPass.cpp | 666 unsigned NewReg = 0;
669 NewReg, IsDstPhys)) {
679 VirtRegPairs.push_back(NewReg);
682 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
684 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
685 VirtRegPairs.push_back(NewReg);
686 Reg = NewReg;
[all...] |
| RegisterCoalescer.cpp | 616 unsigned NewReg = NewDstMO.getReg();
617 if (NewReg != IntB.reg || !LiveRangeQuery(IntB, AValNo->def).isKill())
680 UseMO.setReg(NewReg);
689 if (TargetRegisterInfo::isPhysicalRegister(NewReg))
690 UseMO.substPhysReg(NewReg, *TRI);
692 UseMO.setReg(NewReg);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 654 unsigned NewReg = optimizeSDPattern(MI);
656 if (NewReg != 0) {
662 << PrintReg(NewReg) << "\n");
663 (*I)->substVirtReg(NewReg, 0, *TRI);
666 Replacements[MI] = NewReg;
|
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 575 unsigned NewReg = RegInfo.createVirtualRegister(TRC);
576 return NewReg;
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 597 Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords());
598 Elts.insert(NewReg);
604 NewReg->addSuperClass(Supers[i], Ranges[i]);
611 if (NewReg->getValue(RV.getNameInit()))
635 NewReg->addValue(*Def->getValue(Field));
644 NewReg->addValue(*DefRV);
649 NewReg->addValue(RV);
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
