| /art/runtime/verifier/ |
| register_line.h | 167 size_t NumRegs() const {
|
| /external/llvm/lib/CodeGen/ |
| RegisterClassInfo.cpp | 82 unsigned NumRegs = RC->getNumRegs();
85 RCI.Order.reset(new MCPhysReg[NumRegs]);
114 RCI.NumRegs = N + CSRAlias.size();
115 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
128 if (StressRA && RCI.NumRegs > StressRA)
129 RCI.NumRegs = StressRA;
133 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
141 for (unsigned I = 0; I != RCI.NumRegs; ++I)
|
| VirtRegMap.cpp | 67 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
68 Virt2PhysMap.resize(NumRegs);
69 Virt2StackSlotMap.resize(NumRegs);
70 Virt2SplitMap.resize(NumRegs);
|
| ExecutionDepsFix.cpp | 134 const unsigned NumRegs;
149 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
251 assert(unsigned(rx) < NumRegs && "Invalid index");
263 assert(unsigned(rx) < NumRegs && "Invalid index");
274 assert(unsigned(rx) < NumRegs && "Invalid index");
306 for (unsigned rx = 0; rx != NumRegs; ++rx)
330 for (unsigned rx = 0; rx != NumRegs; ++rx)
346 LiveRegs = new LiveReg[NumRegs];
349 for (unsigned rx = 0; rx != NumRegs; ++rx) {
380 for (unsigned rx = 0; rx != NumRegs; ++rx)
[all...] |
| LiveVariables.cpp | 426 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) {
505 unsigned NumRegs = TRI->getNumRegs();
506 PhysRegDef = new MachineInstr*[NumRegs];
507 PhysRegUse = new MachineInstr*[NumRegs];
509 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
510 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
640 for (unsigned i = 0; i != NumRegs; ++i)
644 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
645 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0)
[all...] |
| MachineLICM.cpp | 496 unsigned NumRegs = TRI->getNumRegs();
497 BitVector PhysRegDefs(NumRegs); // Regs defined once in the loop.
498 BitVector PhysRegClobbers(NumRegs); // Regs defined more than once.
533 BitVector TermRegs(NumRegs);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| RegisterClassInfo.h | 30 unsigned NumRegs;
37 : Tag(0), NumRegs(0), ProperSubClass(false), MinCost(0),
41 return makeArrayRef(Order.get(), NumRegs);
88 return get(RC).NumRegs;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 234 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
235 for (unsigned i = 0; i != NumRegs; ++i) {
|
| LegalizeDAG.cpp | 337 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
351 for (unsigned i = 1; i < NumRegs; i++) {
460 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
471 for (unsigned i = 1; i < NumRegs; i++) {
[all...] |
| LegalizeIntegerTypes.cpp | 720 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
721 // The argument is passed as NumRegs registers of type RegVT.
723 SmallVector<SDValue, 8> Parts(NumRegs);
724 for (unsigned i = 0; i < NumRegs; ++i) {
737 for (unsigned i = 1; i < NumRegs; ++i) {
[all...] |
| SelectionDAGBuilder.cpp | 234 unsigned NumRegs =
237 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
238 NumParts = NumRegs; // Silence a compiler warning.
535 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
540 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
541 NumParts = NumRegs; // Silence a compiler warning.
620 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
622 for (unsigned i = 0; i != NumRegs; ++i)
625 Reg += NumRegs;
693 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 386 bool NumRegs = false;
399 NumRegs = true;
403 if (NumRegs)
|
| ARMExpandPseudoInsts.cpp | 107 uint8_t NumRegs; // D registers loaded or stored
381 unsigned NumRegs = TableEntry->NumRegs;
392 if (NumRegs > 1 && TableEntry->copyAllListRegs)
394 if (NumRegs > 2 && TableEntry->copyAllListRegs)
396 if (NumRegs > 3 && TableEntry->copyAllListRegs)
446 unsigned NumRegs = TableEntry->NumRegs;
467 if (NumRegs > 1 && TableEntry->copyAllListRegs)
469 if (NumRegs > 2 && TableEntry->copyAllListRegs
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMLoadStoreOptimizer.cpp | 290 unsigned NumRegs = Regs.size();
291 if (NumRegs <= 1)
300 else if (Offset == -4 * (int)NumRegs + 4 && haveIBAndDA)
302 else if (Offset == -4 * (int)NumRegs && isNotVFP)
313 if (NumRegs <= 2)
320 NewBase = Regs[NumRegs-1].first;
352 for (unsigned i = 0; i != NumRegs; ++i)
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 156 unsigned NumRegs; // Number of entries in the array
251 NumRegs = NR;
315 assert(RegNo < NumRegs &&
360 return NumRegs;
406 assert(RegNo < NumRegs &&
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 233 unsigned NumRegs; // Number of registers used for this argument.
236 ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
|
| MipsISelLowering.cpp | [all...] |
| /external/v8/src/ |
| frames.cc | [all...] |
| /external/chromium_org/v8/src/ |
| frames.cc | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 792 unsigned NumRegs;
802 : NumRegs(0), AddRecCost(0), NumIVMuls(0), NumBaseAdds(0), ImmCost(0),
812 return ((NumRegs | AddRecCost | NumIVMuls | NumBaseAdds
814 || ((NumRegs & AddRecCost & NumIVMuls & NumBaseAdds
821 return NumRegs == ~0u;
882 ++NumRegs;
[all...] |
