| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 198 SDValue Op0, Op1;
202 if (!SelectADDRrr(Op, Op0, Op1))
203 SelectADDRri(Op, Op0, Op1);
207 OutOps.push_back(Op0);
|
| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| Execution.cpp | [all...] |
| /external/llvm/lib/IR/ |
| AutoUpgrade.cpp | 272 Value *Op0 = CI->getArgOperand(0);
293 Rep = Builder.CreateShuffleVector(Op0, Op0, ConstantVector::get(Idxs));
|
| Instructions.cpp | 62 const char *SelectInst::areInvalidOperands(Value *Op0, Value *Op1, Value *Op2) {
66 if (VectorType *VT = dyn_cast<VectorType>(Op0->getType())) {
68 if (VT->getElementType() != Type::getInt1Ty(Op0->getContext()))
76 } else if (Op0->getType() != Type::getInt1Ty(Op0->getContext())) {
[all...] |
| Verifier.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 247 MachineOperand &Op0 = MI->getOperand(0);
248 unsigned Reg0 = Op0.getReg();
251 // Handle instructions that have a prediate register in op0
|
| HexagonISelDAGToDAG.cpp | 846 SDValue OP0;
856 OP0 = Sext0;
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| CorrelatedValuePropagation.cpp | 163 Value *Op0 = C->getOperand(0);
164 if (isa<Instruction>(Op0) &&
165 cast<Instruction>(Op0)->getParent() == C->getParent())
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 289 SDValue Op0, Op1;
293 if (!SelectAddr(Op, Op0, Op1))
298 OutOps.push_back(Op0);
|
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 261 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
266 if (Op0 == X86::AX && Op1 == X86::AL)
270 if (Op0 == X86::EAX && Op1 == X86::AX)
274 if (Op0 == X86::RAX && Op1 == X86::EAX)
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
31 if (isa<Constant>(Op0))
37 if (Instruction *Res = FoldShiftByConstant(Op0, CUI, I))
312 Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, ConstantInt *Op1,
320 CanEvaluateShifted(Op0, Op1->getZExtValue(), isLeftShift, *this)) {
322 " to eliminate shift:\n IN: " << *Op0 << "\n SH: " << I <<"\n");
325 GetShiftedValue(Op0, Op1->getZExtValue(), isLeftShift, *this));
331 uint32_t TypeBits = Op0->getType()->getScalarSizeInBits();
338 return ReplaceInstUsesWith(I, Constant::getNullValue(Op0->getType()));
345 if (BinaryOperator *BO = dyn_cast<BinaryOperator>(Op0))
[all...] |
| InstCombineAddSub.cpp | [all...] |
| InstCombineCalls.cpp | 598 Value *Op0 = Builder->CreateBitCast(II->getArgOperand(0),
602 Value *Result = UndefValue::get(Op0->getType());
617 Builder->CreateExtractElement(Idx < 16 ? Op0 : Op1,
[all...] |
| InstCombineCasts.cpp | [all...] |
| InstCombineMulDivRem.cpp | 119 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
121 if (Value *V = SimplifyMulInst(Op0, Op1, TD))
128 return BinaryOperator::CreateNeg(Op0, I.getName());
163 if (Op0->hasOneUse() &&
164 match(Op0, m_Add(m_Value(X), m_ConstantInt(C1)))) {
178 if (Op0->hasOneUse()) {
181 if (match(Op0, m_Sub(m_Value(Y), m_Value(X))))
183 else if (match(Op0, m_Add(m_Value(Y), m_ConstantInt(C1))))
197 if (SelectInst *SI = dyn_cast<SelectInst>(Op0))
201 if (isa<PHINode>(Op0))
[all...] |
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.cpp | 776 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name, where the bits
786 uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
792 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
814 uint32_t Op0 = (Bits >> 14) & 0x3;
822 if (Op0 != 3 || (CRn != 11 && CRn != 15)) {
827 assert(Op0 == 3 && (CRn == 11 || CRn == 15) && "Invalid generic sysreg");
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 364 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
366 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
371 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
373 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Analysis/ |
| ValueTracking.cpp | 46 static void ComputeMaskedBitsAddSub(bool Add, Value *Op0, Value *Op1, bool NSW,
51 if (ConstantInt *CLHS = dyn_cast<ConstantInt>(Op0)) {
81 llvm::ComputeMaskedBits(Op0, LHSKnownZero, LHSKnownOne, TD, Depth+1);
132 static void ComputeMaskedBitsMul(Value *Op0, Value *Op1, bool NSW,
138 ComputeMaskedBits(Op0, KnownZero2, KnownOne2, TD, Depth+1);
146 if (Op0 == Op1) {
161 isKnownNonZero(Op0, TD, Depth)) ||
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 398 unsigned Op0 = getRegForValue(I->getOperand(0));
399 if (Op0 == 0) // Unhandled operand. Halt "fast" selection and bail.
423 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
435 ISDOpcode, Op0, Op0IsKill, CF);
453 Op0, Op0IsKill,
789 unsigned Op0 = getRegForValue(I->getOperand(0));
790 if (Op0 == 0)
805 ResultReg).addReg(Op0);
811 ResultReg = FastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
[all...] |
| TargetLowering.cpp | [all...] |
| /external/llvm/lib/ExecutionEngine/ |
| ExecutionEngine.cpp | 576 Constant *Op0 = CE->getOperand(0);
580 GenericValue Result = getConstantValue(Op0);
589 GenericValue GV = getConstantValue(Op0);
595 GenericValue GV = getConstantValue(Op0);
601 GenericValue GV = getConstantValue(Op0);
608 GenericValue GV = getConstantValue(Op0);
614 GenericValue GV = getConstantValue(Op0);
619 GenericValue GV = getConstantValue(Op0);
634 GenericValue GV = getConstantValue(Op0);
650 GenericValue GV = getConstantValue(Op0);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 401 SDValue Op0 = N->getOperand(0);
406 CurDAG->ComputeMaskedBits(Op0, LKZ, LKO);
413 unsigned Op0Opc = Op0.getOpcode();
422 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
423 Op0.getOperand(0).getOpcode() == ISD::SRL) {
426 std::swap(Op0, Op1);
434 std::swap(Op0, Op1);
461 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 269 // If Op0 is null, then Node is a constant that can be loaded using:
273 // If Op0 is nonnull, then Node can be implemented using:
275 // (Opcode (Opcode Op0 UpperVal) LowerVal)
276 SDNode *splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0,
363 // The base or index of AM is equivalent to Op0 + Op1, where IsBase selects
366 SDValue Op0, ConstantSDNode *Op1) {
370 changeComponent(AM, IsBase, Op0);
389 SDValue Op0 = N.getOperand(0);
392 unsigned Op0Code = Op0->getOpcode();
398 return expandAdjDynAlloc(AM, IsBase, Op0);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | [all...] |
