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    Searched defs:RegIndex (Results 1 - 4 of 4) sorted by null

  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
R600ISelLowering.cpp 99 int64_t RegIndex = MI->getOperand(1).getImm();
100 unsigned ConstantReg = AMDGPU::R600_CReg32RegClass.getRegister(RegIndex);
261 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
262 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
282 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
283 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
  /external/llvm/lib/Target/R600/
AMDGPUIndirectAddressing.cpp 98 unsigned RegIndex = MI.getOperand(2).getImm();
100 unsigned Address = TII->calculateIndirectAddress(RegIndex, Channel);
248 unsigned RegIndex = MI.getOperand(2).getImm();
250 unsigned Address = TII->calculateIndirectAddress(RegIndex, Channel);
R600ISelLowering.cpp 500 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
501 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
534 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
535 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
    [all...]
  /external/mesa3d/src/gallium/drivers/radeon/
R600ISelLowering.cpp 99 int64_t RegIndex = MI->getOperand(1).getImm();
100 unsigned ConstantReg = AMDGPU::R600_CReg32RegClass.getRegister(RegIndex);
261 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
262 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
282 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
283 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);

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