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    Searched defs:RegInfo (Results 1 - 25 of 41) sorted by null

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  /external/llvm/lib/Target/NVPTX/
NVPTXInstrInfo.h 28 const NVPTXRegisterInfo RegInfo;
32 virtual const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
NVPTXPrologEpilogPass.cpp 110 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
210 (RegInfo->needsStackRealignment(Fn) && MFI->getObjectIndexEnd() != 0))
  /external/llvm/lib/Target/X86/
X86FrameLowering.cpp 48 const TargetRegisterInfo *RegInfo = TM.getRegisterInfo();
51 RegInfo->needsStackRealignment(MF) ||
316 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
320 int stackGrowth = -RegInfo->getSlotSize();
487 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
488 unsigned FramePtr = RegInfo->getFrameRegister(MF);
489 unsigned StackPtr = RegInfo->getStackRegister();
650 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
664 unsigned SlotSize = RegInfo->getSlotSize();
665 unsigned FramePtr = RegInfo->getFrameRegister(MF)
    [all...]
  /external/llvm/include/llvm/CodeGen/
FunctionLoweringInfo.h 56 MachineRegisterInfo *RegInfo;
MachineFunction.h 82 // RegInfo - Information about each register in use in the function.
83 MachineRegisterInfo *RegInfo;
167 MachineRegisterInfo &getRegInfo() { return *RegInfo; }
168 const MachineRegisterInfo &getRegInfo() const { return *RegInfo; }
SelectionDAGISel.h 49 MachineRegisterInfo *RegInfo;
  /external/llvm/lib/Target/Sparc/
SparcInstrInfo.cpp 382 MachineRegisterInfo &RegInfo = MF->getRegInfo();
384 GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
  /external/llvm/lib/Target/ARM/
Thumb1FrameLowering.cpp 52 const Thumb1RegisterInfo *RegInfo =
71 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
74 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
86 const Thumb1RegisterInfo *RegInfo =
96 unsigned FramePtr = RegInfo->getFrameRegister(MF);
97 unsigned BasePtr = RegInfo->getBaseRegister();
109 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
114 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
185 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
198 if (RegInfo->needsStackRealignment(MF)
    [all...]
ARMFrameLowering.cpp 43 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
53 RegInfo->needsStackRealignment(MF) ||
137 const ARMBaseRegisterInfo *RegInfo =
149 unsigned FramePtr = RegInfo->getFrameRegister(MF);
293 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) {
327 if (RegInfo->hasBasePointer(MF)) {
330 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
335 RegInfo->getBaseRegister())
354 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
364 unsigned FramePtr = RegInfo->getFrameRegister(MF)
    [all...]
  /external/llvm/lib/Target/Mips/Disassembler/
MipsDisassembler.cpp 38 MCDisassembler(STI), RegInfo(Info), isBigEndian(bigEndian) {}
42 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
45 OwningPtr<const MCRegisterInfo> RegInfo;
  /external/llvm/lib/Target/Mips/
Mips16ISelDAGToDAG.cpp 72 MachineRegisterInfo &RegInfo = MF.getRegInfo();
79 V0 = RegInfo.createVirtualRegister(RC);
80 V1 = RegInfo.createVirtualRegister(RC);
81 V2 = RegInfo.createVirtualRegister(RC);
Mips16InstrInfo.cpp 268 // MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
269 // unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
270 // unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
433 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
434 unsigned Reg = RegInfo.createVirtualRegister(RC);
MipsSEISelDAGToDAG.cpp 115 MachineRegisterInfo &RegInfo = MF.getRegInfo();
126 V0 = RegInfo.createVirtualRegister(RC);
127 V1 = RegInfo.createVirtualRegister(RC);
MipsSEFrameLowering.cpp 120 const MipsRegisterInfo &RegInfo =
123 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
127 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
140 const MipsRegisterInfo &RegInfo =
143 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
149 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
163 const MipsRegisterInfo &RegInfo =
166 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
170 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
171 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi)
    [all...]
MipsSEInstrInfo.cpp 338 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
355 unsigned Reg = RegInfo.createVirtualRegister(RC);
MipsSEISelLowering.cpp 770 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
799 unsigned VR2 = RegInfo.createVirtualRegister(RC);
805 unsigned VR1 = RegInfo.createVirtualRegister(RC);
  /external/llvm/lib/Target/XCore/Disassembler/
XCoreDisassembler.cpp 32 OwningPtr<const MCRegisterInfo> RegInfo;
35 MCDisassembler(STI), RegInfo(Info) {}
45 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
  /external/llvm/lib/Target/XCore/
XCoreFrameLowering.cpp 358 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
377 if (RegInfo->requiresRegisterScavenging(MF)) {
  /external/llvm/lib/CodeGen/
PrologEpilogInserter.cpp 208 const TargetRegisterInfo *RegInfo = F.getTarget().getRegisterInfo();
213 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs(&F);
250 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
253 if (RegInfo->hasReservedSpillSlot(F, Reg, FrameIdx)) {
563 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
566 RegInfo->useFPForScavengingIndex(Fn) &&
567 !RegInfo->needsStackRealignment(Fn));
674 (RegInfo->needsStackRealignment(Fn) && MFI->getObjectIndexEnd() != 0))
    [all...]
MachineBasicBlock.cpp 81 // Make sure the instructions have their operands in the reginfo lists.
82 MachineRegisterInfo &RegInfo = MF.getRegInfo();
85 I->AddRegOperandsToUseLists(RegInfo);
    [all...]
MachineFunction.cpp 58 RegInfo = new (Allocator) MachineRegisterInfo(TM);
60 RegInfo = 0;
95 if (RegInfo) {
96 RegInfo->~MachineRegisterInfo();
97 Allocator.Deallocate(RegInfo);
324 if (RegInfo) {
325 OS << (RegInfo->isSSA() ? "SSA" : "Post SSA");
326 if (!RegInfo->tracksLiveness())
343 if (RegInfo && !RegInfo->livein_empty())
    [all...]
RegAllocGreedy.cpp 125 // RegInfo - Keep additional information about each live range.
126 struct RegInfo {
132 RegInfo() : Stage(RS_New), Cascade(0) {}
135 IndexedMap<RegInfo, VirtReg2IndexFunctor> ExtraRegInfo;
    [all...]
  /external/llvm/lib/Target/AArch64/
AArch64FrameLowering.cpp 356 const AArch64RegisterInfo *RegInfo =
381 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs();
AArch64InstrInfo.cpp 784 MachineRegisterInfo &RegInfo = MF->getRegInfo();
785 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass);
  /external/llvm/lib/Target/AArch64/Disassembler/
AArch64Disassembler.cpp 41 OwningPtr<const MCRegisterInfo> RegInfo;
46 : MCDisassembler(STI), RegInfo(Info) {
59 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }

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