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    Searched defs:SrcIdx (Results 1 - 5 of 5) sorted by null

  /external/llvm/lib/CodeGen/
RegisterCoalescer.h 42 /// SrcIdx - The sub-register index of the old SrcReg in the new coalesced
44 unsigned SrcIdx;
63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
113 unsigned getSrcIdx() const { return SrcIdx; }
TwoAddressInstructionPass.cpp 128 unsigned SrcIdx, unsigned DstIdx,
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RegisterCoalescer.cpp 254 SrcIdx = DstIdx = 0;
302 SrcIdx, DstIdx);
307 SrcIdx = DstSub;
324 if (DstIdx && !SrcIdx) {
326 std::swap(SrcIdx, DstIdx);
345 std::swap(SrcIdx, DstIdx);
369 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
383 return TRI.composeSubRegIndices(SrcIdx, SrcSub) ==
739 unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx();
799 TII->reMaterialize(*MBB, MII, DstReg, SrcIdx, DefMI, *TRI)
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  /external/llvm/lib/Target/R600/
AMDGPUISelDAGToDAG.cpp 181 int SrcIdx = I.getOperandNo();
184 // list, so we need to increment the SrcIdx, since
187 SrcIdx++;
190 SelIdx = TII->getSelIdx(I->getMachineOpcode(), SrcIdx);
241 SrcIdx--;
246 if (i == SrcIdx) {
  /external/llvm/lib/Transforms/InstCombine/
InstCombineVectorOps.cpp 258 int SrcIdx = SVI->getMaskValue(Elt->getZExtValue());
263 if (SrcIdx < 0)
265 if (SrcIdx < (int)LHSWidth)
268 SrcIdx -= LHSWidth;
274 SrcIdx, false));
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