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    Searched defs:SubReg (Results 1 - 5 of 5) sorted by null

  /external/llvm/lib/CodeGen/
MachineInstrBundle.cpp 175 unsigned SubReg = *SubRegs;
176 if (LocalDefSet.insert(SubReg))
177 LocalDefs.push_back(SubReg);
LiveVariables.cpp 198 unsigned SubReg = *SubRegs;
199 MachineInstr *Def = PhysRegDef[SubReg];
204 LastDefReg = SubReg;
252 unsigned SubReg = *SubRegs;
253 if (Processed.count(SubReg))
255 if (PartDefRegs.count(SubReg))
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
262 PhysRegDef[SubReg] = LastPartialDef;
263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
291 unsigned SubReg = *SubRegs
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  /external/llvm/lib/Target/R600/
R600OptimizeVectorRegisters.cpp 12 /// common data and/or have enough undef subreg using swizzle abilities.
187 unsigned SubReg = (*It).first;
194 .addReg(SubReg)
196 UpdatedRegToChan[SubReg] = Chan;
  /external/llvm/lib/Target/ARM/
ARMAsmPrinter.cpp 535 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
537 O << ARMInstPrinter::getRegisterName(SubReg);
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  /external/llvm/utils/TableGen/
CodeGenRegisters.cpp 257 // Expand any composed subreg indices.
259 // qsub_1 subreg, add a dsub_2 subreg. Keep growing Indices and process
260 // expanded subreg indices recursively.
275 // Add I->second as a name for the subreg SRI->second, assuming it is
288 // Consider this subreg sequence:
299 // dsub_1, dsub_2] subregs without necessarily having a qsub_1 subreg. The
311 // Compute the inverse SubReg -> Idx map.
429 const CodeGenRegister *SubReg = I->second;
430 const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs
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