| /art/compiler/dex/ |
| local_value_numbering.cc | 466 int base_reg = (opcode == Instruction::IPUT_WIDE) ? 2 : 1; local
467 uint16_t base = GetOperandValue(mir->ssa_rep->uses[base_reg]);
|
| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | 1070 int base_reg = ((lir->opcode == kThumb2LdrdPcRel8) || (lir->opcode == kThumb2LdrPcRel12)) local
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/ |
| radeon_state_init.c | 423 uint32_t base_reg; local
435 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break;
436 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break;
438 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break;
444 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_state_init.c | 423 uint32_t base_reg; local
435 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break;
436 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break;
438 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break;
444 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));
[all...] |
| /external/chromium_org/v8/src/x64/ |
| disasm-x64.cc | 363 int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); } function in class:disasm::DisassemblerX64
[all...] |
| macro-assembler-x64.cc | 702 Register base_reg = r15; local
703 Move(base_reg, next_address);
704 movq(prev_next_address_reg, Operand(base_reg, kNextOffset));
705 movq(prev_limit_reg, Operand(base_reg, kLimitOffset));
706 addl(Operand(base_reg, kLevelOffset), Immediate(1));
757 subl(Operand(base_reg, kLevelOffset), Immediate(1));
758 movq(Operand(base_reg, kNextOffset), prev_next_address_reg);
759 cmpq(prev_limit_reg, Operand(base_reg, kLimitOffset));
820 movq(Operand(base_reg, kLimitOffset), prev_limit_reg);
[all...] |
| /external/qemu/ |
| gdbstub.c | 258 int base_reg; member in struct:GDBRegisterState
[all...] |
| /external/v8/src/x64/ |
| disasm-x64.cc | 358 int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); } function in class:disasm::DisassemblerX64
[all...] |
| macro-assembler-x64.cc | 698 Register base_reg = r15; local
699 movq(base_reg, next_address);
700 movq(prev_next_address_reg, Operand(base_reg, kNextOffset));
701 movq(prev_limit_reg, Operand(base_reg, kLimitOffset));
702 addl(Operand(base_reg, kLevelOffset), Immediate(1));
721 subl(Operand(base_reg, kLevelOffset), Immediate(1));
722 movq(Operand(base_reg, kNextOffset), prev_next_address_reg);
723 cmpq(prev_limit_reg, Operand(base_reg, kLimitOffset));
745 movq(Operand(base_reg, kLimitOffset), prev_limit_reg);
[all...] |
