1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the MIPS implementation of the TargetRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "mips-reg-info" 15 16 #include "MipsRegisterInfo.h" 17 #include "Mips.h" 18 #include "MipsAnalyzeImmediate.h" 19 #include "MipsInstrInfo.h" 20 #include "MipsMachineFunction.h" 21 #include "MipsSubtarget.h" 22 #include "llvm/ADT/BitVector.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/ValueTypes.h" 28 #include "llvm/DebugInfo.h" 29 #include "llvm/IR/Constants.h" 30 #include "llvm/IR/Type.h" 31 #include "llvm/Support/CommandLine.h" 32 #include "llvm/Support/Debug.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/raw_ostream.h" 35 #include "llvm/Target/TargetFrameLowering.h" 36 #include "llvm/Target/TargetInstrInfo.h" 37 #include "llvm/Target/TargetMachine.h" 38 #include "llvm/Target/TargetOptions.h" 39 40 #define GET_REGINFO_TARGET_DESC 41 #include "MipsGenRegisterInfo.inc" 42 43 using namespace llvm; 44 45 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST) 46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {} 47 48 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; } 49 50 51 unsigned 52 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 53 MachineFunction &MF) const { 54 switch (RC->getID()) { 55 default: 56 return 0; 57 case Mips::GPR32RegClassID: 58 case Mips::GPR64RegClassID: 59 case Mips::DSPRegsRegClassID: { 60 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 61 return 28 - TFI->hasFP(MF); 62 } 63 case Mips::FGR32RegClassID: 64 return 32; 65 case Mips::AFGR64RegClassID: 66 return 16; 67 case Mips::FGR64RegClassID: 68 return 32; 69 } 70 } 71 72 //===----------------------------------------------------------------------===// 73 // Callee Saved Registers methods 74 //===----------------------------------------------------------------------===// 75 76 /// Mips Callee Saved Registers 77 const uint16_t* MipsRegisterInfo:: 78 getCalleeSavedRegs(const MachineFunction *MF) const { 79 if (Subtarget.isSingleFloat()) 80 return CSR_SingleFloatOnly_SaveList; 81 else if (!Subtarget.hasMips64()) 82 return CSR_O32_SaveList; 83 else if (Subtarget.isABI_N32()) 84 return CSR_N32_SaveList; 85 86 assert(Subtarget.isABI_N64()); 87 return CSR_N64_SaveList; 88 } 89 90 const uint32_t* 91 MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const { 92 if (Subtarget.isSingleFloat()) 93 return CSR_SingleFloatOnly_RegMask; 94 else if (!Subtarget.hasMips64()) 95 return CSR_O32_RegMask; 96 else if (Subtarget.isABI_N32()) 97 return CSR_N32_RegMask; 98 99 assert(Subtarget.isABI_N64()); 100 return CSR_N64_RegMask; 101 } 102 103 const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() { 104 return CSR_Mips16RetHelper_RegMask; 105 } 106 107 BitVector MipsRegisterInfo:: 108 getReservedRegs(const MachineFunction &MF) const { 109 static const uint16_t ReservedGPR32[] = { 110 Mips::ZERO, Mips::K0, Mips::K1, Mips::SP 111 }; 112 113 static const uint16_t ReservedGPR64[] = { 114 Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64 115 }; 116 117 BitVector Reserved(getNumRegs()); 118 typedef TargetRegisterClass::const_iterator RegIter; 119 120 for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I) 121 Reserved.set(ReservedGPR32[I]); 122 123 for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I) 124 Reserved.set(ReservedGPR64[I]); 125 126 if (Subtarget.hasMips64()) { 127 // Reserve all registers in AFGR64. 128 for (RegIter Reg = Mips::AFGR64RegClass.begin(), 129 EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg) 130 Reserved.set(*Reg); 131 } else { 132 // Reserve all registers in FGR64. 133 for (RegIter Reg = Mips::FGR64RegClass.begin(), 134 EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg) 135 Reserved.set(*Reg); 136 } 137 // Reserve FP if this function should have a dedicated frame pointer register. 138 if (MF.getTarget().getFrameLowering()->hasFP(MF)) { 139 if (Subtarget.inMips16Mode()) 140 Reserved.set(Mips::S0); 141 else { 142 Reserved.set(Mips::FP); 143 Reserved.set(Mips::FP_64); 144 } 145 } 146 147 // Reserve hardware registers. 148 Reserved.set(Mips::HWR29); 149 Reserved.set(Mips::HWR29_64); 150 151 // Reserve DSP control register. 152 Reserved.set(Mips::DSPPos); 153 Reserved.set(Mips::DSPSCount); 154 Reserved.set(Mips::DSPCarry); 155 Reserved.set(Mips::DSPEFI); 156 Reserved.set(Mips::DSPOutFlag); 157 158 // Reserve RA if in mips16 mode. 159 if (Subtarget.inMips16Mode()) { 160 Reserved.set(Mips::RA); 161 Reserved.set(Mips::RA_64); 162 Reserved.set(Mips::T0); 163 Reserved.set(Mips::T1); 164 } 165 166 // Reserve GP if small section is used. 167 if (Subtarget.useSmallSection()) { 168 Reserved.set(Mips::GP); 169 Reserved.set(Mips::GP_64); 170 } 171 172 return Reserved; 173 } 174 175 bool 176 MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { 177 return true; 178 } 179 180 bool 181 MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 182 return true; 183 } 184 185 // FrameIndex represent objects inside a abstract stack. 186 // We must replace FrameIndex with an stack/frame pointer 187 // direct reference. 188 void MipsRegisterInfo:: 189 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, 190 unsigned FIOperandNum, RegScavenger *RS) const { 191 MachineInstr &MI = *II; 192 MachineFunction &MF = *MI.getParent()->getParent(); 193 194 DEBUG(errs() << "\nFunction : " << MF.getName() << "\n"; 195 errs() << "<--------->\n" << MI); 196 197 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 198 uint64_t stackSize = MF.getFrameInfo()->getStackSize(); 199 int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 200 201 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n" 202 << "spOffset : " << spOffset << "\n" 203 << "stackSize : " << stackSize << "\n"); 204 205 eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset); 206 } 207 208 unsigned MipsRegisterInfo:: 209 getFrameRegister(const MachineFunction &MF) const { 210 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 211 bool IsN64 = Subtarget.isABI_N64(); 212 213 if (Subtarget.inMips16Mode()) 214 return TFI->hasFP(MF) ? Mips::S0 : Mips::SP; 215 else 216 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) : 217 (IsN64 ? Mips::SP_64 : Mips::SP); 218 219 } 220 221 unsigned MipsRegisterInfo:: 222 getEHExceptionRegister() const { 223 llvm_unreachable("What is the exception register"); 224 } 225 226 unsigned MipsRegisterInfo:: 227 getEHHandlerRegister() const { 228 llvm_unreachable("What is the exception handler register"); 229 } 230
