| /external/eigen/bench/ |
| check_cache_queries.cpp | 65 int ways = (abcd[1] & 0xFFC00000) >> 22; // B[31:22] local
69 int cache_size = (ways+1) * (partitions+1) * (line_size+1) * (sets+1);
73 cout << "cache[" << cache_id << "].ways = " << ways << "\n"; local
|
| /bionic/libc/kernel/arch-mips/asm/ |
| cpu-info.h | 26 unsigned char ways; member in struct:cache_desc
|
| /development/ndk/platforms/android-9/arch-mips/include/asm/ |
| cpu-info.h | 26 unsigned char ways; member in struct:cache_desc
|
| /external/kernel-headers/original/asm-mips/ |
| cpu-info.h | 23 unsigned char ways; /* Number of ways */ member in struct:cache_desc
|
| /external/lzma/Asm/x86/ |
| AesOpt.asm | 52 ways equ 4
define
53 ways16 equ (ways * 16)
57 rept ways
107 sub rN, ways
110 add rN, ways
202 rept ways
215 sub rN, ways
218 add rN, ways
|
| /prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/asm/ |
| cpu-info.h | 26 unsigned char ways; member in struct:cache_desc
|
| /prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/asm/ |
| cpu-info.h | 26 unsigned char ways; member in struct:cache_desc
|
| /prebuilts/ndk/9/platforms/android-14/arch-mips/usr/include/asm/ |
| cpu-info.h | 26 unsigned char ways; member in struct:cache_desc
|
| /prebuilts/ndk/9/platforms/android-18/arch-mips/usr/include/asm/ |
| cpu-info.h | 26 unsigned char ways; member in struct:cache_desc
|
| /prebuilts/ndk/9/platforms/android-9/arch-mips/usr/include/asm/ |
| cpu-info.h | 26 unsigned char ways; member in struct:cache_desc
|
| /external/eigen/Eigen/src/Core/util/ |
| Memory.h | 776 int ways = (abcd[1] & 0xFFC00000) >> 22; // B[31:22] local
781 int cache_size = (ways+1) * (partitions+1) * (line_size+1) * (sets+1);
807 case 0x0A: l1 = 8; break; // 0Ah data L1 cache, 8 KB, 2 ways, 32 byte lines
808 case 0x0C: l1 = 16; break; // 0Ch data L1 cache, 16 KB, 4 ways, 32 byte lines
809 case 0x0E: l1 = 24; break; // 0Eh data L1 cache, 24 KB, 6 ways, 64 byte lines
810 case 0x10: l1 = 16; break; // 10h data L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64)
811 case 0x15: l1 = 16; break; // 15h code L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64)
812 case 0x2C: l1 = 32; break; // 2Ch data L1 cache, 32 KB, 8 ways, 64 byte lines
813 case 0x30: l1 = 32; break; // 30h code L1 cache, 32 KB, 8 ways, 64 byte lines
814 case 0x60: l1 = 16; break; // 60h data L1 cache, 16 KB, 8 ways, 64 byte lines, sectore
[all...] |
