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    Searched refs:CPU_TLB_SIZE (Results 1 - 12 of 12) sorted by null

  /external/qemu/
cpu-defs.h 77 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
109 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
110 target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
softmmu_template.h 113 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
170 if ((invalidate_cache == 2) && (index < CPU_TLB_SIZE)) {
201 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
288 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
346 if ((invalidate_cache == 2) && (index < CPU_TLB_SIZE)) {
376 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
softmmu_header.h 91 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
112 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
137 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
exec-all.h 394 page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
exec.c     [all...]
  /external/qemu/memcheck/
memcheck_util.c 185 target_ulong index = (start >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
186 const target_ulong to = ((end - 1) >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE-1);
  /external/qemu/tcg/x86_64/
tcg-target.c 593 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
788 tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
    [all...]
  /external/qemu/tcg/arm/
tcg-target.c 987 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
996 TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1);
    [all...]
  /external/qemu/tcg/sparc/
tcg-target.c 774 tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
986 tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
    [all...]
  /external/qemu/tcg/hppa/
tcg-target.c 905 r1 &= CPU_TLB_SIZE - 1;
918 if (check_fit_tl(offset + CPU_TLB_SIZE, 14)) {
    [all...]
  /external/qemu/tcg/i386/
tcg-target.c 1026 (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS, 0);
    [all...]
  /external/qemu/target-mips/
op_helper.c     [all...]

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