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    Searched refs:FCR0_REV (Results 1 - 2 of 2) sorted by null

/external/qemu/target-mips/
translate_init.c	50 #define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV)) 323 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), 341 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), 386 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV), 413 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV), 439 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
cpu.h	85 #define FCR0_REV 0

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