| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 442 /// FLOG, FLOG2, FLOG10, FEXP, FEXP2,
446 FLOG, FLOG2, FLOG10, FEXP, FEXP2,
[all...] |
| /ndk/sources/host-tools/nawk-20071023/ |
| awk.h | 118 #define FLOG 4
|
| lex.c | 71 { "log", FLOG, BLTIN },
|
| run.c | [all...] |
| /external/llvm/lib/CodeGen/ |
| BasicTargetTransformInfo.cpp | 442 case Intrinsic::log: ISD = ISD::FLOG; break;
|
| TargetLoweringBase.cpp | 700 setOperationAction(ISD::FLOG , MVT::f16, Expand);
710 setOperationAction(ISD::FLOG , MVT::f32, Expand);
720 setOperationAction(ISD::FLOG , MVT::f64, Expand);
730 setOperationAction(ISD::FLOG , MVT::f128, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 147 case ISD::FLOG: return "flog";
|
| LegalizeVectorOps.cpp | 235 case ISD::FLOG:
|
| LegalizeFloatTypes.cpp | 77 case ISD::FLOG: R = SoftenFloatRes_FLOG(N); break;
[all...] |
| LegalizeVectorTypes.cpp | 77 case ISD::FLOG:
533 case ISD::FLOG:
[all...] |
| LegalizeDAG.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 188 setOperationAction(ISD::FLOG, MVT::f32, Expand);
189 setOperationAction(ISD::FLOG, MVT::f64, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 335 setOperationAction(ISD::FLOG, MVT::f32, Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 496 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
514 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
531 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 403 setOperationAction(ISD::FLOG, VT, Expand);
[all...] |
