| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 442 /// FLOG, FLOG2, FLOG10, FEXP, FEXP2,
446 FLOG, FLOG2, FLOG10, FEXP, FEXP2,
[all...] |
| /external/llvm/lib/CodeGen/ |
| BasicTargetTransformInfo.cpp | 444 case Intrinsic::log2: ISD = ISD::FLOG2; break;
|
| TargetLoweringBase.cpp | 701 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
711 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
721 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
731 setOperationAction(ISD::FLOG2, MVT::f128, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 148 case ISD::FLOG2: return "flog2";
|
| LegalizeVectorOps.cpp | 236 case ISD::FLOG2:
|
| LegalizeFloatTypes.cpp | 78 case ISD::FLOG2: R = SoftenFloatRes_FLOG2(N); break;
[all...] |
| LegalizeVectorTypes.cpp | 79 case ISD::FLOG2:
535 case ISD::FLOG2:
[all...] |
| LegalizeDAG.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 48 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 191 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
192 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 336 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 497 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
515 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
532 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 405 setOperationAction(ISD::FLOG2, VT, Expand);
[all...] |
