| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 441 /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
445 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
[all...] |
| /external/llvm/lib/CodeGen/ |
| BasicTargetTransformInfo.cpp | 452 case Intrinsic::pow: ISD = ISD::FPOW; break;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 181 case ISD::FPOW: return "fpow";
|
| LegalizeVectorOps.cpp | 234 case ISD::FPOW:
|
| LegalizeFloatTypes.cpp | 87 case ISD::FPOW: R = SoftenFloatRes_FPOW(N); break;
[all...] |
| LegalizeVectorTypes.cpp | 102 case ISD::FPOW:
563 case ISD::FPOW:
[all...] |
| LegalizeDAG.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 47 setOperationAction(ISD::FPOW, MVT::f32, Legal);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 197 setOperationAction(ISD::FPOW, MVT::f32, Expand);
198 setOperationAction(ISD::FPOW, MVT::f64, Expand);
224 setOperationAction(ISD::FPOW, MVT::f128, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 333 setOperationAction(ISD::FPOW, MVT::f32, Expand);
334 setOperationAction(ISD::FPOW, MVT::f64, Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 495 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
513 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
530 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 130 setOperationAction(ISD::FPOW , MVT::f64, Expand);
136 setOperationAction(ISD::FPOW , MVT::f32, Expand);
425 setOperationAction(ISD::FPOW, VT, Expand);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
