| /external/chromium_org/v8/src/mips/ |
| constants-mips.cc | 331 case LWL:
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| constants-mips.h | 286 LWL = ((4 << 3) + 2) << kOpcodeShift,
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| simulator-mips.cc | [all...] |
| assembler-mips.cc | 1406 void Assembler::lwl(Register rd, const MemOperand& rs) { function in class:v8::Assembler
[all...] |
| /external/v8/src/mips/ |
| constants-mips.cc | 325 case LWL:
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| constants-mips.h | 283 LWL = ((4 << 3) + 2) << kOpcodeShift,
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| simulator-mips.cc | [all...] |
| assembler-mips.cc | 1399 void Assembler::lwl(Register rd, const MemOperand& rs) { function in class:v8::Assembler
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 156 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
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| MipsISelLowering.cpp | 183 case MipsISD::LWL: return "MipsISD::LWL";
[all...] |
| /external/valgrind/main/none/tests/mips32/ |
| MIPS32int.stdout.exp | 278 LWL
279 lwl $t0, 0($t1) :: rt 0x1f000000
280 lwl $t0, 4($t1) :: rt 0x00000000
281 lwl $t0, 8($t1) :: rt 0x03000000
282 lwl $t0, 12($t1) :: rt 0xff000000
283 lwl $t0, 16($t1) :: rt 0x2f000000
284 lwl $t0, 20($t1) :: rt 0x2b000000
285 lwl $t0, 24($t1) :: rt 0x2b000000
286 lwl $t0, 28($t1) :: rt 0x2a000000
287 lwl $t0, 32($t1) :: rt 0x3e00000
[all...] |
