| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.h | 124 uint32_t Op2) = 0;
224 ADC(int cc, int s, int Rd, int Rn, uint32_t Op2) {
225 dataProcessing(opADC, cc, s, Rd, Rn, Op2);
228 ADD(int cc, int s, int Rd, int Rn, uint32_t Op2) {
229 dataProcessing(opADD, cc, s, Rd, Rn, Op2);
232 AND(int cc, int s, int Rd, int Rn, uint32_t Op2) {
233 dataProcessing(opAND, cc, s, Rd, Rn, Op2);
236 BIC(int cc, int s, int Rd, int Rn, uint32_t Op2) {
237 dataProcessing(opBIC, cc, s, Rd, Rn, Op2);
240 EOR(int cc, int s, int Rd, int Rn, uint32_t Op2) {
[all...] |
| MIPSAssembler.cpp | 418 int s, int Rd, int Rn, uint32_t Op2)
434 if (dataProcAdrModes(Op2, src) == SRC_REG) {
443 if (dataProcAdrModes(Op2, src, true) == SRC_REG) {
452 if (dataProcAdrModes(Op2, src, true) == SRC_REG) {
460 if (dataProcAdrModes(Op2, src) == SRC_REG) {
468 if (dataProcAdrModes(Op2, src) == SRC_REG) {
476 if (dataProcAdrModes(Op2, src) == SRC_IMM) {
486 if (dataProcAdrModes(Op2, src) == SRC_IMM) {
495 if (Op2 < AMODE_REG) { // op2 is reg # in this cas
[all...] |
| ARMAssemblerProxy.h | 81 uint32_t Op2);
|
| ARMAssemblerProxy.cpp | 161 int Rd, int Rn, uint32_t Op2)
163 mTarget->dataProcessing(opcode, cc, s, Rd, Rn, Op2);
|
| ARMAssembler.h | 92 uint32_t Op2);
|
| ARMAssembler.cpp | 217 int s, int Rd, int Rn, uint32_t Op2)
219 *mPC++ = (cc<<28) | (opcode<<21) | (s<<20) | (Rn<<16) | (Rd<<12) | Op2;
|
| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 252 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
265 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
270 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
280 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
358 unsigned Op1, Op2;
359 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
364 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
371 unsigned Op1, Op2;
372 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
377 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder)
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetSelectionDAGInfo.h | 59 SDValue Op1, SDValue Op2,
76 SDValue Op1, SDValue Op2,
92 SDValue Op1, SDValue Op2,
|
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 60 SDValue Op1, SDValue Op2,
|
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | 526 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
532 Ops.push_back(Op2);
[all...] |
| ISDOpcodes.h | [all...] |
| FastISel.h | 278 unsigned Op2, bool Op2IsKill);
|
| SelectionDAGNodes.h | 744 const SDValue &Op2) {
750 Ops[2].setInitial(Op2);
758 const SDValue &Op2, const SDValue &Op3) {
764 Ops[2].setInitial(Op2);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 581 SDValue Op2 = Op.getOperand(2);
584 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
620 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
627 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
628 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
659 SDValue Op2 = Op.getOperand(2);
687 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
[all...] |
| SelectionDAG.cpp | 268 /// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function
271 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2,
273 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
277 unsigned Op = Op1 | Op2; // Combine all of the condition bits.
292 /// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This
295 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2,
297 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3)
302 ISD::CondCode Result = ISD::CondCode(Op1 & Op2);
751 SDValue Op1, SDValue Op2,
756 SDValue Ops[] = { Op1, Op2 };
[all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 152 ICToken Op2 = OperandStack.pop_back_val();
159 Val = Op1.second + Op2.second;
163 Val = Op1.second - Op2.second;
167 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
169 Val = Op1.second * Op2.second;
173 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
175 assert (Op2.second != 0 && "Division by zero!");
176 Val = Op1.second / Op2.second;
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 299 MachineOperand Op2 = MI->getOperand(S2);
300 ChangeOpInto(MI->getOperand(S1), Op2);
|
| HexagonHardwareLoops.cpp | 524 const MachineOperand &Op2 = CondI->getOperand(2);
528 if (Op2.isImm() || Op1.getReg() == IVReg)
529 EndValue = &Op2;
[all...] |
| /external/llvm/lib/Analysis/ |
| ConstantFolding.cpp | [all...] |
| /external/llvm/include/llvm/Analysis/ |
| ScalarEvolution.h | 594 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2,
599 Ops.push_back(Op2);
612 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2,
617 Ops.push_back(Op2);
[all...] |
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.cpp | 776 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name, where the bits
786 uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
791 Ops[4].getAsInteger(10, Op2);
792 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
818 uint32_t Op2 = Bits & 0x7;
831 + "_c" + utostr(CRm) + "_" + utostr(Op2);
[all...] |
| /external/llvm/include/llvm/Support/ |
| PatternMatch.h | [all...] |
| /external/llvm/lib/AsmParser/ |
| LLParser.cpp | [all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCompares.cpp | [all...] |
