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  /external/llvm/lib/CodeGen/
AllocationOrder.cpp 43 dbgs() << ' ' << PrintReg(Hints[I], TRI);
LiveRegMatrix.cpp 73 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
74 << " to " << PrintReg(PhysReg, TRI) << ':');
88 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
89 << " from " << PrintReg(PhysReg, TRI) << ':');
RegAllocFast.cpp 285 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI)
286 << " in " << PrintReg(LR.PhysReg, TRI));
442 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is already used in instr.\n");
451 DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding "
452 << PrintReg(PhysReg, TRI) << " is reserved already.\n");
462 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is disabled.\n");
491 DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to "
492 << PrintReg(PhysReg, TRI) << "\n");
546 DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from "
552 DEBUG(dbgs() << "\tRegister: " << PrintReg(*I, TRI) << "\n")
    [all...]
RegisterCoalescer.cpp 480 DEBUG(dbgs() << "Extending: " << PrintReg(IntB.reg, TRI));
    [all...]
VirtRegMap.cpp 121 OS << '[' << PrintReg(Reg, TRI) << " -> "
122 << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
130 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
MachineRegisterInfo.cpp 135 errs() << PrintReg(Reg, getTargetRegisterInfo())
143 errs() << PrintReg(Reg, getTargetRegisterInfo())
149 errs() << PrintReg(Reg, getTargetRegisterInfo())
155 errs() << PrintReg(Reg, getTargetRegisterInfo())
RegAllocBase.cpp 102 << ':' << PrintReg(VirtReg->reg) << ' ' << *VirtReg << '\n');
InlineSpiller.cpp 320 OS << "spill " << PrintReg(SVI.SpillReg) << ':'
484 DEBUG(dbgs() << "Cached value " << PrintReg(UseReg) << ':'
489 DEBUG(dbgs() << "Tracing value " << PrintReg(UseReg) << ':'
501 DEBUG(dbgs() << " " << PrintReg(Reg) << ':' << VNI->id << '@' << VNI->def
588 DEBUG(dbgs() << "copy of " << PrintReg(SrcReg) << ':'
661 DEBUG(dbgs() << "Value " << PrintReg(Reg) << ':' << VNI->id << '@'
686 DEBUG(dbgs() << "Stale interval: " << PrintReg(SVI.SpillReg) << '\n');
693 DEBUG(dbgs() << "Stale value: " << PrintReg(SVI.SpillReg) << '\n');
    [all...]
RegAllocGreedy.cpp 473 DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n');
488 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost
519 << PrintReg(PrevReg, TRI) << " to " << PrintReg(PhysReg, TRI)
649 DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI)
724 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR "
725 << PrintReg(CSR, TRI) << '\n');
    [all...]
LiveIntervalUnion.cpp 88 << PrintReg(SI.value()->reg, TRI);
RegisterClassInfo.cpp 142 dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
RegAllocPBQP.cpp 488 DEBUG(dbgs() << "VREG " << PrintReg(vreg, tri) << " -> "
498 DEBUG(dbgs() << "VREG " << PrintReg(vreg, tri) << " -> SPILLED (Cost: "
506 DEBUG(dbgs() << PrintReg((*itr)->reg, tri) << " ");
TargetRegisterInfo.cpp 36 void PrintReg::print(raw_ostream &OS) const {
MachineVerifier.cpp 419 *OS << PrintReg(LI.reg, TRI);
430 *OS << PrintReg(LI.reg, TRI);
    [all...]
PHIElimination.cpp 258 DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi);
580 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
ScheduleDAG.cpp 351 dbgs() << " Reg=" << PrintReg(I->getReg(), G->TRI);
371 dbgs() << " Reg=" << PrintReg(I->getReg(), G->TRI);
LiveRangeEdit.cpp 398 DEBUG(dbgs() << "Inflated " << PrintReg(LI.reg) << " to "
LiveInterval.cpp 688 OS << "Clean " << PrintReg(LI->reg) << " updater: " << *LI << '\n';
694 OS << PrintReg(LI->reg) << " updater with gap = " << (ReadI - WriteI)
MachineFunction.cpp 347 OS << PrintReg(I->first, TRI);
349 OS << " in " << PrintReg(I->second, TRI);
    [all...]
RegisterPressure.cpp 97 dbgs() << PrintReg(LiveInRegs[i], TRI) << " ";
101 dbgs() << PrintReg(LiveOutRegs[i], TRI) << " ";
MachineInstr.cpp 267 OS << PrintReg(getReg(), TRI, getSubReg());
    [all...]
LiveIntervalAnalysis.cpp 150 OS << PrintReg(Reg) << " = " << getInterval(Reg) << '\n';
776 dbgs() << PrintReg(LI.reg);
    [all...]
  /external/llvm/include/llvm/Target/
TargetRegisterInfo.h     [all...]
  /external/llvm/lib/Target/ARM/
A15SDOptimizer.cpp 286 DEBUG(dbgs() << PrintReg(FullReg) << "\n");
662 << PrintReg(NewReg) << "\n");
  /external/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGDumper.cpp 423 OS << ' ' << PrintReg(R->getReg(), G ? G->getTarget().getRegisterInfo() :0);

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