| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/sys/ |
| reg.h | 35 # define R10 7
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/sys/ |
| reg.h | 35 # define R10 7
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/sys/ |
| reg.h | 35 # define R10 7
|
| /art/runtime/arch/arm/ |
| registers_arm.h | 37 R10 = 10,
|
| /external/kernel-headers/original/asm-x86/ |
| ptrace-abi.h | 36 #define R10 56
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.h | 27 // are still a few places that R11 and R10 are hard wired.
36 #define HEXAGON_RESERVED_REG_1 Hexagon::R10
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/asm/ |
| ptrace-abi.h | 36 #define R10 56
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/asm/ |
| ptrace-abi.h | 36 #define R10 56
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/asm/ |
| ptrace-abi.h | 36 #define R10 56
|
| /prebuilts/ndk/4/platforms/android-5/arch-x86/usr/include/asm/ |
| ptrace-abi.h | 47 #define R10 56
|
| /prebuilts/ndk/4/platforms/android-8/arch-x86/usr/include/asm/ |
| ptrace-abi.h | 47 #define R10 56
|
| /prebuilts/ndk/6/platforms/android-9/arch-x86/usr/include/asm/ |
| ptrace-abi.h | 47 #define R10 56
|
| /prebuilts/ndk/7/platforms/android-14/arch-x86/usr/include/asm/ |
| ptrace-abi.h | 47 #define R10 56
|
| /prebuilts/ndk/7/platforms/android-9/arch-x86/usr/include/asm/ |
| ptrace-abi.h | 47 #define R10 56
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 45 case R8: case R9: case R10: case R11:
56 case R8: case R9: case R10: case R11:
|
| /art/compiler/jni/quick/arm/ |
| calling_convention_arm.cc | 129 callee_save_regs_.push_back(ArmManagedRegister::FromCoreRegister(R10));
136 result = 1 << R5 | 1 << R6 | 1 << R7 | 1 << R8 | 1 << R10 | 1 << R11 | 1 << LR;
|
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 66 XCore::R8, XCore::R9, XCore::R10, XCore::LR,
81 Reserved.set(XCore::R10);
260 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
|
| XCoreFrameLowering.cpp | 151 // Save R10 to the stack.
153 storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4, dl, TII);
154 // R10 is live-in. It is killed at the spill.
155 MBB.addLiveIn(XCore::R10);
161 unsigned FramePtr = XCore::R10;
184 unsigned FramePtr = XCore::R10;
204 // Restore R10
207 loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset, dl, TII);
|
| /external/valgrind/main/coregrind/m_sigframe/ |
| sigframe-arm-linux.c | 148 SC2(r10,R10);
327 REST(r10,R10);
|
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.cpp | 572 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
609 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
645 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
681 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
682 return X86::R10;
|
| X86FrameLowering.cpp | 104 X86::R8, X86::R9, X86::R10, X86::R11, 0
[all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.h | 171 ENTRY(R10) \
189 ENTRY(R10) \
|
| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.h | 50 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15,
58 LIST(R7), LIST(R8), LIST(R9), LIST(R10), LIST(R11), LIST(R12),
|
| /external/valgrind/main/VEX/auxprogs/ |
| genoffsets.c | 110 GENOFFSET(AMD64,amd64,R10);
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86BaseInfo.h | 668 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
|
