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  /external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/lc3b/tests/
lc3b-mp22NC.asm 7 LD R7, R0, ADATA3F-AA
10 ST R7, R1, BDATA3D-BB
11 ST R7, R1, BDATA3F-BB
12 ST R7, R1, BDATA3C-BB
17 RSHFL R6, R7, 8
18 STB R7, R4, 0
22 LD R7, R0, ADATA39-AA
23 ST R7, R1, BDATA38-BB
25 ST R7, R1, BDATA39-BB
26 ST R7, R1, BDATA3A-BB
    [all...]
  /art/runtime/arch/arm/
registers_arm.h 34 R7 = 7,
  /art/compiler/jni/quick/arm/
calling_convention_arm.cc 127 callee_save_regs_.push_back(ArmManagedRegister::FromCoreRegister(R7));
136 result = 1 << R5 | 1 << R6 | 1 << R7 | 1 << R8 | 1 << R10 | 1 << R11 | 1 << LR;
  /art/compiler/utils/arm/
managed_register_arm_test.cc 284 EXPECT_EQ(R7, reg.AsRegisterPairHigh());
462 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
484 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
503 reg = ArmManagedRegister::FromCoreRegister(R7);
506 EXPECT_TRUE(reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
528 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
550 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
572 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
594 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
616 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromCoreRegister(R7)));
    [all...]
  /external/llvm/lib/Target/ARM/
ARMBaseRegisterInfo.h 36 /// isARMArea1Register - Returns true if the register is a low register (r0-r7)
42 case R4: case R5: case R6: case R7:
46 // For iOS we want r7 and lr to be next to each other.
Thumb1FrameLowering.cpp 126 case ARM::R7:
ARMFrameLowering.cpp 181 case ARM::R7:
217 // For iOS, FP is R7, which has now been stored in spill area 1.
270 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
273 // mov sp, r7
401 // mov sp, r7
    [all...]
ARMBaseRegisterInfo.cpp 48 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
521 // R7, LR
ARMAsmPrinter.cpp     [all...]
  /external/oprofile/module/ia64/
IA64entry.h 52 .spillsp r6, SW(R6)+16+(off); .spillsp r7, SW(R7)+16+(off); \
  /external/valgrind/main/coregrind/m_sigframe/
sigframe-arm-linux.c 145 SC2(r7,R7);
324 REST(r7,R7);
  /system/core/libpixelflinger/codeflinger/
ARMAssemblerInterface.h 50 R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15,
58 LIST(R7), LIST(R8), LIST(R9), LIST(R10), LIST(R11), LIST(R12),
  /external/llvm/lib/Target/ARM/MCTargetDesc/
ARMBaseInfo.h 207 /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
213 case R4: case R5: case R6: case R7:
  /external/llvm/lib/Target/XCore/
XCoreRegisterInfo.cpp 65 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
  /external/valgrind/main/VEX/auxprogs/
genoffsets.c 155 GENOFFSET(ARM,arm,R7);
166 GENOFFSET(S390X,s390x,r7);
  /external/llvm/lib/Target/PowerPC/AsmParser/
PPCAsmParser.cpp 36 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
47 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
    [all...]
  /art/runtime/
runtime.cc     [all...]
  /external/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp     [all...]
  /external/valgrind/main/memcheck/
mc_machine.c     [all...]
  /external/chromium/third_party/libjingle/source/talk/session/phone/testdata/
video.rtpdump     [all...]
  /external/chromium_org/third_party/libjingle/source/talk/media/testdata/
video.rtpdump     [all...]
h264-svc-99-640x360.rtpdump 261 s???S??W?D?????v?S??????J??????3?h??únC=?{K?i????]?]n??n???*???}z?jI'??#??C??t??????Z_?A?zS$>m??H?? 3?S_??}w|N"?C??Q8?_??G??G?"U??j? R7?????B ?? y?????JB&?}????-?!o???,??h?\?dOT?+gC?":???}?.\ \?????;??1????????R?vw?@
    [all...]
  /external/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp     [all...]
  /external/llvm/lib/Target/ARM/Disassembler/
ARMDisassembler.cpp     [all...]
  /external/llvm/test/MC/ARM/
basic-thumb2-instructions.s 23 adc r3, r7, #0x00550055
25 adc r9, r7, #0xa5a5a5a5
33 @ CHECK: adc r3, r7, #5570645 @ encoding: [0x47,0xf1,0x55,0x13]
35 @ CHECK: adc r9, r7, #2779096485 @ encoding: [0x47,0xf1,0xa5,0x39]
82 add r1, r7, #0xcbcbcbcb
105 @ CHECK: add.w r1, r7, #3419130827 @ encoding: [0x07,0xf1,0xcb,0x31]
119 adds r7, r3, r1, lsl #31
127 @ CHECK: adds.w r7, r3, r1, lsl #31 @ encoding: [0x13,0xeb,0xc1,0x77]
167 ands r2, r1, r7, lsl #1
173 @ CHECK: ands.w r2, r1, r7, lsl #1 @ encoding: [0x11,0xea,0x47,0x02
    [all...]

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