OpenGrok
Home
Sort by relevance
Sort by last modified time
Full Search
Definition
Symbol
File Path
History
|
|
Help
Searched
refs:Reg0
(Results
1 - 11
of
11
) sorted by null
/external/llvm/include/llvm/MC/
MCRegisterInfo.h
524
uint16_t
Reg0
;
527
MCRegUnitRootIterator() :
Reg0
(0), Reg1(0) {}
530
Reg0
= MCRI->RegUnitRoots[RegUnit][0];
536
return
Reg0
;
541
return
Reg0
;
547
Reg0
= Reg1;
/external/llvm/lib/Target/Hexagon/
HexagonPeephole.cpp
248
unsigned
Reg0
= Op0.getReg();
249
const TargetRegisterClass *RC0 = MRI->getRegClass(
Reg0
);
253
if (TargetRegisterInfo::isVirtualRegister(
Reg0
)) {
255
if (unsigned PeepholeSrc = PeepholeMap.lookup(
Reg0
)) {
/external/llvm/lib/CodeGen/
TargetInstrInfo.cpp
135
unsigned
Reg0
= HasDef ? MI->getOperand(0).getReg() : 0;
145
if (HasDef &&
Reg0
== Reg1 &&
148
Reg0
= Reg2;
150
} else if (HasDef &&
Reg0
== Reg2 &&
153
Reg0
= Reg1;
164
MI->getOperand(0).setReg(
Reg0
);
/external/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp
[
all
...]
Thumb2SizeReduction.cpp
643
unsigned
Reg0
= MI->getOperand(0).getReg();
649
if (!isARMLowRegister(
Reg0
) || !isARMLowRegister(Reg1)
652
if (
Reg0
!= Reg2) {
655
if (Reg1 !=
Reg0
)
662
} else if (
Reg0
!= Reg1) {
666
CommOpIdx1 != 1 || MI->getOperand(CommOpIdx2).getReg() !=
Reg0
)
672
if (Entry.LowRegs2 && !isARMLowRegister(
Reg0
))
[
all
...]
ARMAsmPrinter.cpp
470
unsigned
Reg0
= TRI->getSubReg(RegBegin, ARM::gsub_0);
471
O << ARMInstPrinter::getRegisterName(
Reg0
) << ", ";;
[
all
...]
/external/llvm/lib/Target/AArch64/InstPrinter/
AArch64InstPrinter.cpp
328
unsigned
Reg0
= MI->getOperand(0).getReg();
331
if (isStackReg(
Reg0
) || isStackReg(Reg1)) {
334
if (
Reg0
== AArch64::XSP || Reg1 == AArch64::XSP)
/external/llvm/lib/Target/ARM/InstPrinter/
ARMInstPrinter.cpp
[
all
...]
/external/llvm/lib/Target/Mips/
MipsSEFrameLowering.cpp
323
unsigned
Reg0
=
329
std::swap(
Reg0
, Reg1);
332
MCCFIInstruction::createOffset(CSLabel,
Reg0
, Offset));
/external/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp
171
unsigned
Reg0
= MI->getOperand(0).getReg();
179
if (
Reg0
== Reg1) {
193
unsigned
Reg0
= ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
196
.addReg(
Reg0
, RegState::Define | getDeadRegState(Reg0IsDead))
[
all
...]
/external/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp
[
all
...]
Completed in 288 milliseconds