| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 80 bool contains(unsigned Reg1, unsigned Reg2) const {
81 return contains(Reg1) && contains(Reg2);
525 uint16_t Reg1;
527 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {}
531 Reg1 = MCRI->RegUnitRoots[RegUnit][1];
547 Reg0 = Reg1;
548 Reg1 = 0;
|
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 115 unsigned Reg1, bool isKill1,
117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
|
| X86FastISel.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| AggressiveAntiDepBreaker.h | 101 // UnionGroups - Union Reg1's and Reg2's groups to form a new
104 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
|
| TargetInstrInfo.cpp | 136 unsigned Reg1 = MI->getOperand(Idx1).getReg();
145 if (HasDef && Reg0 == Reg1 &&
153 Reg0 = Reg1;
167 MI->getOperand(Idx2).setReg(Reg1);
|
| AggressiveAntiDepBreaker.cpp | 79 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2)
85 unsigned Group1 = GetGroup(Reg1);
[all...] |
| StrongPHIElimination.cpp | 438 void StrongPHIElimination::unionRegs(unsigned Reg1, unsigned Reg2) {
439 Node *Node1 = RegNodeMap[Reg1]->getLeader();
|
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.h | 120 unsigned Reg1, unsigned Reg2) const;
|
| Mips16InstrInfo.cpp | 266 unsigned Reg1, unsigned Reg2) const {
269 // unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass);
272 // li reg1, constant
274 // add reg1, reg1, reg2
275 // move sp, reg1
278 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
282 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
283 MIB3.addReg(Reg1);
287 MIB4.addReg(Reg1, RegState::Kill)
[all...] |
| MipsSEFrameLowering.cpp | 325 unsigned Reg1 =
329 std::swap(Reg0, Reg1);
334 MCCFIInstruction::createOffset(CSLabel, Reg1, Offset + 4));
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 329 unsigned Reg1 = MI->getOperand(1).getReg();
331 if (isStackReg(Reg0) || isStackReg(Reg1)) {
334 if (Reg0 == AArch64::XSP || Reg1 == AArch64::XSP)
|
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 81 bool contains(unsigned Reg1, unsigned Reg2) const {
82 return MC->contains(Reg1, Reg2);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 90 unsigned Reg1, unsigned Reg2);
470 unsigned Reg1, unsigned Reg2) {
476 .addReg(Reg1)
|
| Thumb2SizeReduction.cpp | 644 unsigned Reg1 = MI->getOperand(1).getReg();
649 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
655 if (Reg1 != Reg0)
662 } else if (Reg0 != Reg1) {
[all...] |
| ARMFastISel.cpp | [all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 393 unsigned Reg1 = Reg;
398 .addReg(Reg1, RegState::Kill)
437 unsigned Reg1 = Reg;
443 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
|
| PPCInstrInfo.cpp | 172 unsigned Reg1 = MI->getOperand(1).getReg();
179 if (Reg0 == Reg1) {
198 .addReg(Reg1, getKillRegState(Reg1IsKill))
205 MI->getOperand(2).setReg(Reg1);
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | [all...] |
| /external/llvm/lib/MC/ |
| MCDwarf.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
