| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 77 unsigned RegClass = Desc.OpInfo[OpNo].RegClass;
78 return (AMDGPU::SSrc_32RegClassID == RegClass) ||
79 (AMDGPU::SSrc_64RegClassID == RegClass) ||
80 (AMDGPU::VSrc_32RegClassID == RegClass) ||
81 (AMDGPU::VSrc_64RegClassID == RegClass);
|
| /external/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 125 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
154 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
156 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
157 return scavengeRegister(RegClass, MBBI, SPAdj);
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| RegisterClassInfo.h | 46 OwningArrayPtr<RCInfo> RegClass;
72 const RCInfo &RCI = RegClass[RC->getID()];
|
| MachineRegisterInfo.h | 340 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.h | 36 unsigned RegClass) const;
38 unsigned RegClass, bool &ScalarSlotUsed) const;
|
| SIISelLowering.cpp | 595 /// \brief Test if RegClass is one of the VSrc classes
596 static bool isVSrc(unsigned RegClass) {
597 return AMDGPU::VSrc_32RegClassID == RegClass ||
598 AMDGPU::VSrc_64RegClassID == RegClass;
601 /// \brief Test if RegClass is one of the SSrc classes
602 static bool isSSrc(unsigned RegClass) {
603 return AMDGPU::SSrc_32RegClassID == RegClass ||
604 AMDGPU::SSrc_64RegClassID == RegClass;
696 int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
728 /// \brief Does "Op" fit into register class "RegClass"
[all...] |
| R600InstrInfo.cpp | 689 switch (MI->getDesc().OpInfo->RegClass) {
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 35 const TargetRegisterClass &RegClass,
41 if (RegClass.contains(*AR)) {
53 const TargetRegisterClass &RegClass,
55 char Prefix = &RegClass == &AArch64::GPR32RegClass ? 'w' : 'x';
67 if (RegClass.contains(*AR)) {
|
| AArch64FrameLowering.h | 31 const TargetRegisterClass *RegClass; // E.g. GPR64RegClass
|
| AArch64FrameLowering.cpp | 452 if (PossClasses[ClassIdx].RegClass->contains(Reg))
457 const TargetRegisterClass &TheClass = *PossClasses[ClassIdx].RegClass;
|
| /external/llvm/lib/CodeGen/ |
| RegisterClassInfo.cpp | 42 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
79 RCInfo &RCI = RegClass[RC->getID()];
115 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
|
| MachineRegisterInfo.cpp | 101 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
102 assert(RegClass && "Cannot create register without RegClass!");
103 assert(RegClass->isAllocatable() &&
104 "Virtual register RegClass must be allocatable.");
109 VRegInfo[Reg].first = RegClass;
|
| TargetInstrInfo.cpp | 45 short RegClass = MCID.OpInfo[OpNum].RegClass;
47 return TRI->getPointerRegClass(MF, RegClass);
50 if (RegClass < 0)
54 return TRI->getRegClass(RegClass);
|
| /external/llvm/include/llvm/MC/ |
| MCInstrDesc.h | 59 /// RegClass - This specifies the register class enumeration of the operand
63 int16_t RegClass;
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 432 SDValue RegClass = CurDAG->getTargetConstant(RCID, MVT::i32);
435 const SDValue Ops[] = { RegClass, Node->getOperand(0), LoIdx,
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 253 switch (MI->getDesc().OpInfo->RegClass) {
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 645 llvm_unreachable("Unknown regclass!");
756 llvm_unreachable("Unknown regclass!");
846 if (UseInfo->RegClass /* Kind */ != 1)
849 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
850 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 253 switch (MI->getDesc().OpInfo->RegClass) {
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 179 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
900 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
905 return getReg(RegClass, RegNum);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 278 unsigned &RegClass, unsigned &Cost,
291 RegClass = RC->getID();
300 RegClass = RC->getID();
308 RegClass = RC->getID();
313 RegClass = TLI->getRepRegClassFor(VT)->getID();
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 701 // Verify that all altorder members are regclass members.
[all...] |
| CodeGenDAGPatterns.cpp | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 564 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
[all...] |
