| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 470 { ISD::SETCC, MVT::v2f64, 1 },
471 { ISD::SETCC, MVT::v4f32, 1 },
472 { ISD::SETCC, MVT::v2i64, 1 },
473 { ISD::SETCC, MVT::v4i32, 1 },
474 { ISD::SETCC, MVT::v8i16, 1 },
475 { ISD::SETCC, MVT::v16i8, 1 },
479 { ISD::SETCC, MVT::v4f64, 1 },
480 { ISD::SETCC, MVT::v8f32, 1 },
482 { ISD::SETCC, MVT::v4i64, 4 },
483 { ISD::SETCC, MVT::v8i32, 4 }
[all...] |
| X86ISelLowering.cpp | 226 // X86 is weird, it always uses i8 for shift amounts and setcc results.
517 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
518 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
520 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
521 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
525 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
[all...] |
| X86ISelLowering.h | 93 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
95 SETCC,
97 // Same as SETCC except it's materialized with a sbb and the value is all
101 /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
595 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 62 setTargetDAGCombine(ISD::SETCC);
318 ISD::SETCC,
384 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
403 // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
409 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
415 case ISD::SETCC: {
422 // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
|
| R600ISelLowering.cpp | 48 setOperationAction(ISD::SETCC, MVT::i32, Custom);
252 case ISD::SETCC: return LowerSETCC(Op, DAG);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 62 setTargetDAGCombine(ISD::SETCC);
318 ISD::SETCC,
384 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
403 // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
409 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
415 case ISD::SETCC: {
422 // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
|
| R600ISelLowering.cpp | 48 setOperationAction(ISD::SETCC, MVT::i32, Custom);
252 case ISD::SETCC: return LowerSETCC(Op, DAG);
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 320 /// Much like the scalar select and setcc, each bit in the condition selects
333 /// SetCC operator - This evaluates to a true value iff the condition is
339 SETCC,
490 /// compare, rather than as a combined SetCC node. The operands in order
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.h | 32 SETCC,
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 50 /// SetCC - Operand 0 is condition code, and operand 1 is the flag
52 SETCC,
|
| MSP430ISelLowering.cpp | 112 setOperationAction(ISD::SETCC, MVT::i8, Custom);
113 setOperationAction(ISD::SETCC, MVT::i16, Custom);
196 case ISD::SETCC: return LowerSETCC(Op, DAG);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 114 setOperationAction(ISD::SETCC, MVT::i32, Custom);
115 setOperationAction(ISD::SETCC, MVT::i64, Custom);
116 setOperationAction(ISD::SETCC, MVT::f32, Custom);
117 setOperationAction(ISD::SETCC, MVT::f64, Custom);
232 setOperationAction(ISD::SETCC, MVT::f128, Custom);
285 setOperationAction(ISD::SETCC, MVT::v8i8, Custom);
286 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
287 setOperationAction(ISD::SETCC, MVT::v4i16, Custom);
288 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
289 setOperationAction(ISD::SETCC, MVT::v2i32, Custom)
[all...] |
| AArch64ISelLowering.h | 70 /// which will be produced by a setcc instruction.
73 /// This serves most of the functions of the LLVM SETCC instruction, for two
81 SETCC,
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 78 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
79 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
92 setTargetDAGCombine(ISD::SETCC);
431 if (Intr->getOpcode() == ISD::SETCC) {
433 SDNode *SetCC = Intr;
434 assert(SetCC->getConstantOperandVal(1) == 1);
435 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
437 Intr = SetCC->getOperand(0).getNode();
513 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
560 // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc
[all...] |
| R600ISelLowering.cpp | 53 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
54 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
68 setOperationAction(ISD::SETCC, MVT::i32, Expand);
69 setOperationAction(ISD::SETCC, MVT::f32, Expand);
771 ISD::SETCC,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 221 case ISD::SETCC:
296 else if (Node->getOpcode() == ISD::SETCC)
761 Ops[i] = DAG.getNode(ISD::SETCC, dl,
|
| LegalizeVectorTypes.cpp | 64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
309 // Turn it into a scalar SETCC.
310 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
336 // Turn it into a scalar SETCC.
337 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
513 case ISD::SETCC:
[all...] |
| DAGCombiner.cpp | 549 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
550 // that selects between the values 1 and 0, making it equivalent to a setcc.
556 if (N.getOpcode() == ISD::SETCC) {
575 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
[all...] |
| TargetLowering.cpp | 101 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
107 && "Unsupported setcc type!");
179 default: llvm_unreachable("Do not know how to soften this setcc!");
190 SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
194 NewLHS = DAG.getNode(ISD::SETCC, dl,
[all...] |
| SelectionDAGDumper.cpp | 184 case ISD::SETCC: return "setcc";
284 default: llvm_unreachable("Unknown setcc condition!");
|
| LegalizeDAG.cpp | 46 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
47 /// will attempt merge setcc and brc instructions into brcc's.
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 73 setTargetDAGCombine(ISD::SETCC);
481 SDValue SetCC = N->getOperand(0);
483 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
487 SetCC.getOperand(0), SetCC.getOperand(1), N->getOperand(1),
488 N->getOperand(2), SetCC.getOperand(2));
511 case ISD::SETCC: {
|
| MipsISelLowering.cpp | 221 // setcc operations results (slt, sgt, ...).
234 // Used by legalize types to correctly generate the setcc result.
235 // Without this, every float setcc comes with a AND/OR with the result,
238 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
252 setOperationAction(ISD::SETCC, MVT::f32, Custom);
253 setOperationAction(ISD::SETCC, MVT::f64, Custom);
496 // Creates and returns an FPCmp node from a setcc node.
497 // Returns Op if setcc is not a floating point comparison.
499 // must be a SETCC node
500 if (Op.getOpcode() != ISD::SETCC)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
