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    Searched refs:SRC3 (Results 1 - 10 of 10) sorted by null

/external/bison/lib/
bitset.h	243 /* DST = (SRC1 & SRC2) | SRC3. */ 244 #define bitset_and_or(DST, SRC1, SRC2, SRC3) \ 245 BITSET_AND_OR_ (DST, SRC1, SRC2, SRC3) 247 /* DST = (SRC1 & SRC2) | SRC3. Return non-zero if 248 DST != (SRC1 & SRC2) | SRC3. */ 249 #define bitset_and_or_cmp(DST, SRC1, SRC2, SRC3) \ 250 BITSET_AND_OR_CMP_ (DST, SRC1, SRC2, SRC3) 252 /* DST = (SRC1 & ~SRC2) | SRC3. */ 253 #define bitset_andn_or(DST, SRC1, SRC2, SRC3) \ 254 BITSET_ANDN_OR_ (DST, SRC1, SRC2, SRC3)     [all...]
bbitset.h	168 #define BITSET_CHECK4_(DST, SRC1, SRC2, SRC3) \ 170 || !BITSET_COMPATIBLE_ (DST, SRC3)) abort (); 247 /* DST = (SRC1 & SRC2) | SRC3. Return non-zero if 248 DST != (SRC1 & SRC2) | SRC3. */ 249 #define BITSET_AND_OR_(DST, SRC1, SRC2, SRC3) \ 250 (SRC1)->b.vtable->and_or (DST, SRC1, SRC2, SRC3) 251 #define BITSET_AND_OR_CMP_(DST, SRC1, SRC2, SRC3) \ 252 (SRC1)->b.vtable->and_or_cmp (DST, SRC1, SRC2, SRC3) 254 /* DST = (SRC1 & ~SRC2) | SRC3. Return non-zero if 255 DST != (SRC1 & ~SRC2) | SRC3. *     [all...]
/external/chromium_org/third_party/mesa/src/src/mesa/x86/
x86_xform4.S	44 #define SRC3 REGOFF(12, ESI) 141 FLD_S( SRC3 ) /* F0 F7 F6 F5 F4 */ 143 FLD_S( SRC3 ) /* F1 F0 F7 F6 F5 F4 */ 145 FLD_S( SRC3 ) /* F2 F1 F0 F7 F6 F5 F4 */ 147 FLD_S( SRC3 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */ 232 FLD_S( SRC3 ) /* F2 F6 F5 F4 */ 329 FLD_S( SRC3 ) /* F0 F6 F5 F4 */ 331 FLD_S( SRC3 ) /* F1 F0 F6 F5 F4 */ 333 FLD_S( SRC3 ) /* F2 F1 F0 F6 F5 F4 */ 341 MOV_L( SRC3, EBX     [all...]
x86_cliptest.S	39 #define SRC3 REGOFF(12, ESI) 53 * bit6 = SRC3 < 0 166 FDIV_S( SRC3 ) /* GH: don't care about div-by-zero */ 168 MOV_L( SRC3, EBP ) 334 MOV_L( SRC3, EBP )
x86_xform2.S	44 #define SRC3 REGOFF(12, ESI)
x86_xform3.S	44 #define SRC3 REGOFF(12, ESI)
/external/mesa3d/src/mesa/x86/
x86_xform4.S	44 #define SRC3 REGOFF(12, ESI) 141 FLD_S( SRC3 ) /* F0 F7 F6 F5 F4 */ 143 FLD_S( SRC3 ) /* F1 F0 F7 F6 F5 F4 */ 145 FLD_S( SRC3 ) /* F2 F1 F0 F7 F6 F5 F4 */ 147 FLD_S( SRC3 ) /* F3 F2 F1 F0 F7 F6 F5 F4 */ 232 FLD_S( SRC3 ) /* F2 F6 F5 F4 */ 329 FLD_S( SRC3 ) /* F0 F6 F5 F4 */ 331 FLD_S( SRC3 ) /* F1 F0 F6 F5 F4 */ 333 FLD_S( SRC3 ) /* F2 F1 F0 F6 F5 F4 */ 341 MOV_L( SRC3, EBX     [all...]
x86_cliptest.S	39 #define SRC3 REGOFF(12, ESI) 53 * bit6 = SRC3 < 0 166 FDIV_S( SRC3 ) /* GH: don't care about div-by-zero */ 168 MOV_L( SRC3, EBP ) 334 MOV_L( SRC3, EBP )
x86_xform2.S	44 #define SRC3 REGOFF(12, ESI)
x86_xform3.S	44 #define SRC3 REGOFF(12, ESI)

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