| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 490 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost},
494 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost},
498 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost},
502 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost},
507 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost},
511 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost},
515 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost},
519 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost},
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 176 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 118 // TODO: Implement custom UREM/SREM routines
119 setOperationAction(ISD::SREM, VT, Expand);
179 setOperationAction(ISD::SREM, MVT::v2i64, Expand);
655 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS);
673 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS);
|
| AMDGPUISelLowering.cpp | 90 case ISD::SREM: return LowerSREM(Op, DAG);
|
| /external/llvm/lib/Target/R600/ |
| AMDILISelLowering.cpp | 107 // TODO: Implement custom UREM/SREM routines
108 setOperationAction(ISD::SREM, VT, Expand);
163 setOperationAction(ISD::SREM, MVT::v2i64, Expand);
555 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS);
572 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS);
|
| AMDGPUISelLowering.cpp | 181 case ISD::SREM: return LowerSREM(Op, DAG);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 118 // TODO: Implement custom UREM/SREM routines
119 setOperationAction(ISD::SREM, VT, Expand);
179 setOperationAction(ISD::SREM, MVT::v2i64, Expand);
655 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS);
673 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS);
|
| AMDGPUISelLowering.cpp | 90 case ISD::SREM: return LowerSREM(Op, DAG);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.h | 479 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
|
| SelectionDAGDumper.cpp | 159 case ISD::SREM: return "srem";
|
| LegalizeVectorOps.cpp | 198 case ISD::SREM:
|
| LegalizeVectorTypes.cpp | 108 case ISD::SREM:
571 case ISD::SREM:
[all...] |
| FastISel.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 110 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
[all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 772 case ISD::SREM:
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 159 setOperationAction(ISD::SREM, MVT::i8, Expand);
165 setOperationAction(ISD::SREM, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 138 setOperationAction(ISD::SREM, MVT::i32, Expand);
139 setOperationAction(ISD::SREM, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 288 setOperationAction(ISD::SREM, MVT::i32, Expand);
292 setOperationAction(ISD::SREM, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 109 // PowerPC has no SREM/UREM instructions
110 setOperationAction(ISD::SREM, MVT::i32, Expand);
112 setOperationAction(ISD::SREM, MVT::i64, Expand);
115 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
396 setOperationAction(ISD::SREM, VT, Expand);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 114 setOperationAction(ISD::SREM, VT, Expand);
[all...] |
