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    Searched refs:SUa (Results 1 - 2 of 2) sorted by null

  /external/llvm/lib/CodeGen/
ScheduleDAGInstrs.cpp 553 /// "latest" node that needs a chain edge to SUa.
556 SUnit *SUa, SUnit *SUb, SUnit *ExitSU, unsigned *Depth,
558 if (!SUa || !SUb || SUb == ExitSU)
574 if (SUa->isSucc(SUb) ||
582 MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) {
583 SUb->addPred(SDep(SUa, SDep::MayAliasMem));
592 iterateChainSucc (AA, MFI, SUa, I->getSUnit(), ExitSU, Depth, Visited);
632 SUnit *SUa, SUnit *SUb,
639 MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) {
640 SDep Dep(SUa, isNormalMemory ? SDep::MayAliasMem : SDep::Barrier)
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MachineScheduler.cpp 830 SUnit *SUa = LoadRecords[Idx].SU;
832 if (TII->shouldClusterLoads(SUa->getInstr(), SUb->getInstr(), ClusterLength)
833 && DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
835 DEBUG(dbgs() << "Cluster loads SU(" << SUa->NodeNum << ") - SU("
837 // Copy successor edges from SUa to SUb. Interleaving computation
838 // dependent on SUa can prevent load combining due to register reuse.
839 // Predecessor edges do not need to be copied from SUb to SUa since nearby
842 SI = SUa->Succs.begin(), SE = SUa->Succs.end(); SI != SE; ++SI) {
    [all...]

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