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    Searched refs:SchedClass (Results 1 - 7 of 7) sorted by null

  /external/llvm/include/llvm/Target/
TargetSubtargetInfo.h 49 /// Resolve a SchedClass at runtime, where SchedClass identifies an
51 /// another variant SchedClass, but repeated invocation must quickly terminate
52 /// in a nonvariant SchedClass.
53 virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI,
  /external/llvm/lib/CodeGen/
TargetSchedule.cpp 106 unsigned SchedClass = MI->getDesc().getSchedClass();
107 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
117 SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
118 SCDesc = SchedModel.getSchedClassDesc(SchedClass);
  /external/llvm/include/llvm/CodeGen/
ScheduleDAGInstrs.h 161 if (!SU->SchedClass && SchedModel.hasInstrSchedModel())
162 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
163 return SU->SchedClass;
ScheduleDAG.h 260 const MCSchedClassDesc *SchedClass; // NULL or resolved SchedClass.
312 : Node(node), Instr(0), OrigNode(0), SchedClass(0), NodeNum(nodenum),
326 : Node(0), Instr(instr), OrigNode(0), SchedClass(0), NodeNum(nodenum),
339 : Node(0), Instr(0), OrigNode(0), SchedClass(0), NodeNum(BoundaryID),
  /external/llvm/include/llvm/MC/
MCInstrDesc.h 141 unsigned short SchedClass; // enum identifying instr sched class
552 return SchedClass;
  /external/llvm/utils/TableGen/
SubtargetEmitter.cpp 34 // Each processor has a SchedClassDesc table with an entry for each SchedClass.
828 // Generate the SchedClass table for this processor and update global
851 // A Variant SchedClass has no resources of its own.
872 // Determine if the SchedClass is actually reachable on this processor. If
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonVLIWPacketizer.cpp     [all...]

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