| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 259 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
262 .addMBB(TBB);
267 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
268 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 198 .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
200 .addMBB(TargetBB);
232 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
240 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
242 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
246 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 287 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
292 .addMBB(TBB);
301 .addMBB(TBB);
302 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
|
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 110 MIB.addMBB(TBB);
132 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
139 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
|
| Mips16ISelLowering.cpp | 525 .addMBB(sinkMBB);
542 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
543 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
589 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
606 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
607 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
654 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
671 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
672 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
691 BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(BtOpc)).addMBB(target)
[all...] |
| MipsLongBranch.cpp | 238 MIB.addMBB(MBBOpnd);
294 .append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB))
349 .append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB))
379 .append(BuildMI(*MF, DL, TII->get(Mips::J)).addMBB(TgtMBB))
|
| MipsSEISelLowering.cpp | 796 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
802 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
812 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 272 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
278 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
283 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
|
| MSP430BranchSelector.cpp | 161 I = BuildMI(MBB, I, dl, TII->get(MSP430::Bi)).addMBB(Dest);
|
| MSP430ISelLowering.cpp | [all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 271 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB).addReg(0);
280 .addMBB(TBB)
290 .addMBB(TBB)
292 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB).addReg(0);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 271 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB).addReg(0);
280 .addMBB(TBB)
290 .addMBB(TBB)
292 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB).addReg(0);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonNewValueJump.cpp | 614 .addMBB(jmpTarget);
624 .addMBB(jmpTarget);
631 .addMBB(jmpTarget);
|
| HexagonFixupHwLoops.cpp | 180 .addMBB(MII->getOperand(0).getMBB());
|
| HexagonHardwareLoops.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCBranchSelector.cpp | 182 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
|
| PPCInstrInfo.cpp | 403 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
407 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
410 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
418 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
421 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
422 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineSSAUpdater.cpp | 191 InsertedPHI.addReg(PredValues[i].second).addMBB(PredValues[i].first);
318 MachineInstrBuilder(*Pred->getParent(), PHI).addReg(Val).addMBB(Pred);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMConstantIslandPass.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64BranchFixupPass.cpp | 376 BuildMI(OrigBB, DebugLoc(), TII->get(AArch64::Bimm)).addMBB(NewBB);
589 .addMBB(MI->getOperand(CondBrMBBOperand).getMBB());
|
| AArch64InstrInfo.cpp | 298 BuildMI(&MBB, DL, get(AArch64::Bimm)).addMBB(TBB);
304 MIB.addMBB(TBB);
311 MIB.addMBB(TBB);
313 BuildMI(&MBB, DL, get(AArch64::Bimm)).addMBB(FBB);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGISel.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUIndirectAddressing.cpp | 201 Phi.addMBB(RegBlock);
|
| R600InstrInfo.cpp | 717 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB);
726 .addMBB(TBB)
741 .addMBB(TBB)
743 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB);
[all...] |
