| /external/chromium_org/v8/src/x64/ |
| codegen-x64.h | 116 Register base_reg,
121 : base_reg_(base_reg),
129 Register base_reg,
134 : base_reg_(base_reg),
142 Register base_reg,
147 : base_reg_(base_reg),
|
| disasm-x64.cc | 363 int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); } function in class:disasm::DisassemblerX64
[all...] |
| macro-assembler-x64.cc | 702 Register base_reg = r15; local
703 Move(base_reg, next_address);
704 movq(prev_next_address_reg, Operand(base_reg, kNextOffset));
705 movq(prev_limit_reg, Operand(base_reg, kLimitOffset));
706 addl(Operand(base_reg, kLevelOffset), Immediate(1));
757 subl(Operand(base_reg, kLevelOffset), Immediate(1));
758 movq(Operand(base_reg, kNextOffset), prev_next_address_reg);
759 cmpq(prev_limit_reg, Operand(base_reg, kLimitOffset));
820 movq(Operand(base_reg, kLimitOffset), prev_limit_reg);
[all...] |
| /dalvik/vm/compiler/codegen/x86/libenc/ |
| enc_wrapper.h | 181 int disp, int base_reg, bool isBasePhysical, char* stream);
188 int disp, int base_reg, bool isBasePhysical,
191 int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale,
195 int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale,
198 int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale,
201 int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale,
205 int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale,
209 int disp, int base_reg, bool isBasePhysical, LowOpndRegType type, char* stream);
215 int disp, int base_reg, bool isBasePhysical, char* stream);
217 int disp, int base_reg, bool isBasePhysical, char* stream)
[all...] |
| enc_wrapper.cpp | 196 int disp, int base_reg, bool isBasePhysical, char * stream) {
198 add_m(args, base_reg, disp, size);
243 int disp, int base_reg, bool isBasePhysical,
247 add_m(args, base_reg, disp, size);
257 int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale,
261 add_m_scale(args, base_reg, index_reg, scale, size);
272 int base_reg, bool isBasePhysical, int index_reg, bool isIndexPhysical, int scale,
275 add_m_scale(args, base_reg, index_reg, scale, size);
286 int base_reg, bool isBasePhysical, int disp, int index_reg, bool isIndexPhysical, int scale,
290 add_m_disp_scale(args, base_reg, disp, index_reg, scale, size)
[all...] |
| /dalvik/vm/compiler/codegen/x86/ |
| Lower.h | 609 //LR[reg] = disp + PR[base_reg] or disp + LR[base_reg]
610 void load_effective_addr(int disp, int base_reg, bool isBasePhysical,
612 void load_effective_addr_scale(int base_reg, bool isBasePhysical,
615 void load_fpu_cw(int disp, int base_reg, bool isBasePhysical);
616 void store_fpu_cw(bool checkException, int disp, int base_reg, bool isBasePhysical);
618 void load_fp_stack(LowOp* op, OpndSize size, int disp, int base_reg, bool isBasePhysical);
619 void load_int_fp_stack(OpndSize size, int disp, int base_reg, bool isBasePhysical);
621 void store_fp_stack(LowOp* op, bool pop, OpndSize size, int disp, int base_reg, bool isBasePhysical);
622 void store_int_fp_stack(LowOp* op, bool pop, OpndSize size, int disp, int base_reg, bool isBasePhysical)
[all...] |
| LowerHelper.cpp | 274 int disp, int base_reg) {
275 stream = encoder_mem(m, size, disp, base_reg, true, stream);
280 int disp, int base_reg, bool isBasePhysical) {
284 int regAll = registerAlloc(LowOpndRegType_gp, base_reg, isBasePhysical, true);
287 stream = encoder_mem(m, size, disp, base_reg, isBasePhysical, stream);
421 int disp, int base_reg,
425 stream = encoder_moves_mem_to_reg(size, disp, base_reg, true,
429 stream = encoder_movez_mem_to_reg(size, disp, base_reg, true,
433 stream = encoder_mem_reg(m, size, disp, base_reg, true,
443 int disp, int base_reg, bool isBasePhysical
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/program/ |
| register_allocate.h | 44 unsigned int base_reg, unsigned int reg);
|
| register_allocate.c | 210 * Adds a conflict between base_reg and reg, and also between reg and
211 * anything that base_reg conflicts with.
219 unsigned int base_reg, unsigned int reg)
223 ra_add_reg_conflict(regs, reg, base_reg);
225 for (i = 0; i < regs->regs[base_reg].num_conflicts; i++) {
226 ra_add_reg_conflict(regs, reg, regs->regs[base_reg].conflict_list[i]);
|
| /external/mesa3d/src/mesa/program/ |
| register_allocate.h | 44 unsigned int base_reg, unsigned int reg);
|
| register_allocate.c | 210 * Adds a conflict between base_reg and reg, and also between reg and
211 * anything that base_reg conflicts with.
219 unsigned int base_reg, unsigned int reg)
223 ra_add_reg_conflict(regs, reg, base_reg);
225 for (i = 0; i < regs->regs[base_reg].num_conflicts; i++) {
226 ra_add_reg_conflict(regs, reg, regs->regs[base_reg].conflict_list[i]);
|
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
| brw_vec4_reg_allocate.cpp | 131 for (int base_reg = j;
132 base_reg < j + class_sizes[i];
133 base_reg++) {
134 ra_add_transitive_reg_conflict(brw->vs.regs, base_reg, reg);
|
| brw_fs_reg_allocate.cpp | 119 for (int base_reg = j;
120 base_reg < j + class_sizes[i];
121 base_reg++) {
122 ra_add_transitive_reg_conflict(brw->wm.regs, base_reg, reg);
|
| brw_blorp_blit.cpp | 493 void alloc_push_const_regs(int base_reg);
743 brw_blorp_blit_program::alloc_push_const_regs(int base_reg)
748 brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 2)
[all...] |
| brw_wm_emit.c | [all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vec4_reg_allocate.cpp | 131 for (int base_reg = j;
132 base_reg < j + class_sizes[i];
133 base_reg++) {
134 ra_add_transitive_reg_conflict(brw->vs.regs, base_reg, reg);
|
| brw_fs_reg_allocate.cpp | 119 for (int base_reg = j;
120 base_reg < j + class_sizes[i];
121 base_reg++) {
122 ra_add_transitive_reg_conflict(brw->wm.regs, base_reg, reg);
|
| brw_blorp_blit.cpp | 493 void alloc_push_const_regs(int base_reg);
743 brw_blorp_blit_program::alloc_push_const_regs(int base_reg)
748 brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 2)
[all...] |
| /external/qemu/ |
| gdbstub.c | 258 int base_reg; member in struct:GDBRegisterState
[all...] |
| /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/ |
| radeon_state_init.c | 423 uint32_t base_reg; local
435 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break;
436 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break;
438 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break;
444 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_state_init.c | 423 uint32_t base_reg; local
435 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break;
436 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break;
438 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break;
444 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));
[all...] |
| /art/compiler/dex/ |
| local_value_numbering.cc | 466 int base_reg = (opcode == Instruction::IPUT_WIDE) ? 2 : 1; local
467 uint16_t base = GetOperandValue(mir->ssa_rep->uses[base_reg]);
|
| /external/v8/src/x64/ |
| disasm-x64.cc | 358 int base_reg(int low_bits) { return low_bits | ((rex_ & 0x01) << 3); } function in class:disasm::DisassemblerX64
[all...] |
| macro-assembler-x64.cc | 698 Register base_reg = r15; local
699 movq(base_reg, next_address);
700 movq(prev_next_address_reg, Operand(base_reg, kNextOffset));
701 movq(prev_limit_reg, Operand(base_reg, kLimitOffset));
702 addl(Operand(base_reg, kLevelOffset), Immediate(1));
721 subl(Operand(base_reg, kLevelOffset), Immediate(1));
722 movq(Operand(base_reg, kNextOffset), prev_next_address_reg);
723 cmpq(prev_limit_reg, Operand(base_reg, kLimitOffset));
745 movq(Operand(base_reg, kLimitOffset), prev_limit_reg);
[all...] |
| /art/compiler/dex/quick/arm/ |
| assemble_arm.cc | 1070 int base_reg = ((lir->opcode == kThumb2LdrdPcRel8) || (lir->opcode == kThumb2LdrPcRel12)) local
[all...] |
