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  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv30/
nv30_push.c 40 const void *idxbuf; member in struct:push_context
88 uint8_t *elts = (uint8_t *)ctx->idxbuf + start;
120 uint16_t *elts = (uint16_t *)ctx->idxbuf + start;
152 uint32_t *elts = (uint32_t *)ctx->idxbuf + start;
224 if (nv30->idxbuf.buffer)
225 ctx.idxbuf = nouveau_resource_map_offset(&nv30->base,
226 nv04_resource(nv30->idxbuf.buffer), nv30->idxbuf.offset,
229 ctx.idxbuf = nv30->idxbuf.user_buffer
    [all...]
nv30_vbo.c 456 const unsigned index_size = nv30->idxbuf.index_size;
470 nv30->idxbuf.buffer) {
471 struct nv04_resource *res = nv04_resource(nv30->idxbuf.buffer);
472 unsigned offset = nv30->idxbuf.offset;
507 if (nv30->idxbuf.buffer)
509 nv04_resource(nv30->idxbuf.buffer),
510 nv30->idxbuf.offset, NOUVEAU_BO_RD);
512 data = nv30->idxbuf.user_buffer;
nv30_state.c 422 pipe_resource_reference(&nv30->idxbuf.buffer, ib->buffer);
423 nv30->idxbuf.index_size = ib->index_size;
424 nv30->idxbuf.offset = ib->offset;
425 nv30->idxbuf.user_buffer = ib->user_buffer;
427 pipe_resource_reference(&nv30->idxbuf.buffer, NULL);
428 nv30->idxbuf.user_buffer = NULL;
nv30_context.h 110 struct pipe_index_buffer idxbuf; member in struct:nv30_context
nv30_draw.c 415 const void *map = nv30->idxbuf.user_buffer;
417 pipe_buffer_map(pipe, nv30->idxbuf.buffer,
421 (ubyte *) map + nv30->idxbuf.offset,
422 nv30->idxbuf.index_size);
  /external/mesa3d/src/gallium/drivers/nv30/
nv30_push.c 40 const void *idxbuf; member in struct:push_context
88 uint8_t *elts = (uint8_t *)ctx->idxbuf + start;
120 uint16_t *elts = (uint16_t *)ctx->idxbuf + start;
152 uint32_t *elts = (uint32_t *)ctx->idxbuf + start;
224 if (nv30->idxbuf.buffer)
225 ctx.idxbuf = nouveau_resource_map_offset(&nv30->base,
226 nv04_resource(nv30->idxbuf.buffer), nv30->idxbuf.offset,
229 ctx.idxbuf = nv30->idxbuf.user_buffer
    [all...]
nv30_vbo.c 456 const unsigned index_size = nv30->idxbuf.index_size;
470 nv30->idxbuf.buffer) {
471 struct nv04_resource *res = nv04_resource(nv30->idxbuf.buffer);
472 unsigned offset = nv30->idxbuf.offset;
507 if (nv30->idxbuf.buffer)
509 nv04_resource(nv30->idxbuf.buffer),
510 nv30->idxbuf.offset, NOUVEAU_BO_RD);
512 data = nv30->idxbuf.user_buffer;
nv30_state.c 422 pipe_resource_reference(&nv30->idxbuf.buffer, ib->buffer);
423 nv30->idxbuf.index_size = ib->index_size;
424 nv30->idxbuf.offset = ib->offset;
425 nv30->idxbuf.user_buffer = ib->user_buffer;
427 pipe_resource_reference(&nv30->idxbuf.buffer, NULL);
428 nv30->idxbuf.user_buffer = NULL;
nv30_context.h 110 struct pipe_index_buffer idxbuf; member in struct:nv30_context
nv30_draw.c 415 const void *map = nv30->idxbuf.user_buffer;
417 pipe_buffer_map(pipe, nv30->idxbuf.buffer,
421 (ubyte *) map + nv30->idxbuf.offset,
422 nv30->idxbuf.index_size);
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/
nv50_push.c 16 const void *idxbuf; member in struct:push_context
65 uint8_t *elts = (uint8_t *)ctx->idxbuf + start;
98 uint16_t *elts = (uint16_t *)ctx->idxbuf + start;
131 uint32_t *elts = (uint32_t *)ctx->idxbuf + start;
239 if (nv50->idxbuf.buffer) {
240 ctx.idxbuf = nouveau_resource_map_offset(&nv50->base,
241 nv04_resource(nv50->idxbuf.buffer), nv50->idxbuf.offset,
244 ctx.idxbuf = nv50->idxbuf.user_buffer
    [all...]
nv50_vbo.c 569 const unsigned index_size = nv50->idxbuf.index_size;
579 if (nv50->idxbuf.buffer) {
580 struct nv04_resource *buf = nv04_resource(nv50->idxbuf.buffer);
583 const unsigned base = (buf->offset + nv50->idxbuf.offset) & ~3;
585 start += ((buf->offset + nv50->idxbuf.offset) & 3) >> (index_size >> 1);
587 assert(nouveau_resource_mapped_by_gpu(nv50->idxbuf.buffer));
630 const void *data = nv50->idxbuf.user_buffer;
nv50_state.c 922 if (nv50->idxbuf.buffer)
926 pipe_resource_reference(&nv50->idxbuf.buffer, ib->buffer);
927 nv50->idxbuf.index_size = ib->index_size;
929 nv50->idxbuf.offset = ib->offset;
932 nv50->idxbuf.user_buffer = ib->user_buffer;
935 pipe_resource_reference(&nv50->idxbuf.buffer, NULL);
    [all...]
nv50_context.c 83 pipe_resource_reference(&nv50->idxbuf.buffer, NULL);
  /external/mesa3d/src/gallium/drivers/nv50/
nv50_push.c 16 const void *idxbuf; member in struct:push_context
65 uint8_t *elts = (uint8_t *)ctx->idxbuf + start;
98 uint16_t *elts = (uint16_t *)ctx->idxbuf + start;
131 uint32_t *elts = (uint32_t *)ctx->idxbuf + start;
239 if (nv50->idxbuf.buffer) {
240 ctx.idxbuf = nouveau_resource_map_offset(&nv50->base,
241 nv04_resource(nv50->idxbuf.buffer), nv50->idxbuf.offset,
244 ctx.idxbuf = nv50->idxbuf.user_buffer
    [all...]
nv50_vbo.c 569 const unsigned index_size = nv50->idxbuf.index_size;
579 if (nv50->idxbuf.buffer) {
580 struct nv04_resource *buf = nv04_resource(nv50->idxbuf.buffer);
583 const unsigned base = (buf->offset + nv50->idxbuf.offset) & ~3;
585 start += ((buf->offset + nv50->idxbuf.offset) & 3) >> (index_size >> 1);
587 assert(nouveau_resource_mapped_by_gpu(nv50->idxbuf.buffer));
630 const void *data = nv50->idxbuf.user_buffer;
nv50_state.c 922 if (nv50->idxbuf.buffer)
926 pipe_resource_reference(&nv50->idxbuf.buffer, ib->buffer);
927 nv50->idxbuf.index_size = ib->index_size;
929 nv50->idxbuf.offset = ib->offset;
932 nv50->idxbuf.user_buffer = ib->user_buffer;
935 pipe_resource_reference(&nv50->idxbuf.buffer, NULL);
    [all...]
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nvc0/
nvc0_push.c 16 void *idxbuf; member in struct:push_context
123 uint8_t *restrict elts = (uint8_t *)ctx->idxbuf + start;
164 uint16_t *restrict elts = (uint16_t *)ctx->idxbuf + start;
205 uint32_t *restrict elts = (uint32_t *)ctx->idxbuf + start;
328 ctx.idxbuf =
330 nv04_resource(nvc0->idxbuf.buffer),
331 nvc0->idxbuf.offset, NOUVEAU_BO_RD);
332 if (!ctx.idxbuf)
334 index_size = nvc0->idxbuf.index_size;
338 ctx.idxbuf = NULL
    [all...]
nvc0_vbo_translate.c 18 const void *idxbuf; member in struct:push_context
84 if (nvc0->idxbuf.buffer) {
85 struct nv04_resource *buf = nv04_resource(nvc0->idxbuf.buffer);
86 ctx->idxbuf = nouveau_resource_map_offset(&nvc0->base,
87 buf, nvc0->idxbuf.offset, NOUVEAU_BO_RD);
89 ctx->idxbuf = nvc0->idxbuf.user_buffer;
209 const uint8_t *restrict elts = (uint8_t *)ctx->idxbuf + start;
265 const uint16_t *restrict elts = (uint16_t *)ctx->idxbuf + start;
321 const uint32_t *restrict elts = (uint32_t *)ctx->idxbuf + start
    [all...]
nvc0_vbo.c 507 struct nv04_resource *buf = nv04_resource(nvc0->idxbuf.buffer);
514 PUSH_DATAh(push, buf->address + nvc0->idxbuf.offset);
515 PUSH_DATA (push, buf->address + nvc0->idxbuf.offset);
518 PUSH_DATA (push, nvc0->idxbuf.index_size >> 1);
692 const unsigned index_size = nvc0->idxbuf.index_size;
703 if (nvc0->idxbuf.buffer) {
719 const void *data = nvc0->idxbuf.user_buffer;
nvc0_state.c 842 if (nvc0->idxbuf.buffer)
846 pipe_resource_reference(&nvc0->idxbuf.buffer, ib->buffer);
847 nvc0->idxbuf.index_size = ib->index_size;
849 nvc0->idxbuf.offset = ib->offset;
852 nvc0->idxbuf.user_buffer = ib->user_buffer;
857 pipe_resource_reference(&nvc0->idxbuf.buffer, NULL);
  /external/mesa3d/src/gallium/drivers/nvc0/
nvc0_push.c 16 void *idxbuf; member in struct:push_context
123 uint8_t *restrict elts = (uint8_t *)ctx->idxbuf + start;
164 uint16_t *restrict elts = (uint16_t *)ctx->idxbuf + start;
205 uint32_t *restrict elts = (uint32_t *)ctx->idxbuf + start;
328 ctx.idxbuf =
330 nv04_resource(nvc0->idxbuf.buffer),
331 nvc0->idxbuf.offset, NOUVEAU_BO_RD);
332 if (!ctx.idxbuf)
334 index_size = nvc0->idxbuf.index_size;
338 ctx.idxbuf = NULL
    [all...]
nvc0_vbo_translate.c 18 const void *idxbuf; member in struct:push_context
84 if (nvc0->idxbuf.buffer) {
85 struct nv04_resource *buf = nv04_resource(nvc0->idxbuf.buffer);
86 ctx->idxbuf = nouveau_resource_map_offset(&nvc0->base,
87 buf, nvc0->idxbuf.offset, NOUVEAU_BO_RD);
89 ctx->idxbuf = nvc0->idxbuf.user_buffer;
209 const uint8_t *restrict elts = (uint8_t *)ctx->idxbuf + start;
265 const uint16_t *restrict elts = (uint16_t *)ctx->idxbuf + start;
321 const uint32_t *restrict elts = (uint32_t *)ctx->idxbuf + start
    [all...]
nvc0_vbo.c 507 struct nv04_resource *buf = nv04_resource(nvc0->idxbuf.buffer);
514 PUSH_DATAh(push, buf->address + nvc0->idxbuf.offset);
515 PUSH_DATA (push, buf->address + nvc0->idxbuf.offset);
518 PUSH_DATA (push, nvc0->idxbuf.index_size >> 1);
692 const unsigned index_size = nvc0->idxbuf.index_size;
703 if (nvc0->idxbuf.buffer) {
719 const void *data = nvc0->idxbuf.user_buffer;
nvc0_state.c 842 if (nvc0->idxbuf.buffer)
846 pipe_resource_reference(&nvc0->idxbuf.buffer, ib->buffer);
847 nvc0->idxbuf.index_size = ib->index_size;
849 nvc0->idxbuf.offset = ib->offset;
852 nvc0->idxbuf.user_buffer = ib->user_buffer;
857 pipe_resource_reference(&nvc0->idxbuf.buffer, NULL);

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