| /art/compiler/dex/quick/x86/ |
| utility_x86.cc | 198 LIR* X86Mir2Lir::OpRegMem(OpKind op, int r_dest, int rBase,
218 return NewLIR3(opcode, r_dest, rBase, offset);
307 LIR* X86Mir2Lir::OpMem(OpKind op, int rBase, int disp) {
315 return NewLIR2(opcode, rBase, disp);
345 LIR* X86Mir2Lir::LoadBaseIndexedDisp(int rBase, int r_index, int scale,
402 load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET);
404 if (rBase == r_dest) {
405 load2 = NewLIR3(opcode, r_dest_hi, rBase,
407 load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET);
409 load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET)
[all...] |
| codegen_x86.h | 33 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
34 LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi,
36 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
37 LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
41 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
42 LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi);
43 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
44 LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
146 LIR* OpMem(OpKind op, int rBase, int disp);
152 LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset)
[all...] |
| int_x86.cc | 239 void X86Mir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset) {
240 NewLIR5(kX86Lea32RA, rBase, reg1, reg2, scale, offset);
257 LIR* X86Mir2Lir::OpVldm(int rBase, int count) {
262 LIR* X86Mir2Lir::OpVstm(int rBase, int count) {
|
| /art/compiler/dex/quick/mips/ |
| utility_mips.cc | 336 LIR* MipsMir2Lir::LoadBaseIndexed(int rBase, int r_index, int r_dest,
353 first = NewLIR3(kMipsAddu, t_reg , rBase, r_index);
356 NewLIR3(kMipsAddu, t_reg , rBase, t_reg);
388 LIR* MipsMir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src,
405 first = NewLIR3(kMipsAddu, t_reg , rBase, r_index);
408 NewLIR3(kMipsAddu, t_reg , rBase, t_reg);
434 LIR* MipsMir2Lir::LoadBaseDispBody(int rBase, int displacement, int r_dest,
498 load = res = NewLIR3(opcode, r_dest, displacement, rBase);
501 displacement + LOWORD_OFFSET, rBase);
503 displacement + HIWORD_OFFSET, rBase);
[all...] |
| codegen_mips.h | 33 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
34 LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi,
36 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
37 LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
41 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
42 LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi);
43 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
44 LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
146 LIR* OpMem(OpKind op, int rBase, int disp);
152 LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset)
[all...] |
| call_mips.cc | 48 * addiu rBase, r_RA, <table> - <BaseLabel> ; table relative to BaseLabel
49 addu rEnd, rEnd, rBase ; end of table
52 * beq rBase, rEnd, done
53 * lw r_key, 0(rBase)
54 * addu rBase, 8
56 * lw r_disp, -4(rBase)
103 int rBase = AllocTemp();
104 NewLIR4(kMipsDelta, rBase, 0, reinterpret_cast<uintptr_t>(base_label),
106 OpRegRegReg(kOpAdd, rEnd, rEnd, rBase);
114 LIR* exit_branch = OpCmpBranch(kCondEq, rBase, rEnd, NULL)
[all...] |
| int_mips.cc | 253 void MipsMir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset) {
276 LIR* MipsMir2Lir::OpVldm(int rBase, int count) {
281 LIR* MipsMir2Lir::OpVstm(int rBase, int count) {
|
| /art/compiler/dex/quick/arm/ |
| utility_arm.cc | 642 LIR* ArmMir2Lir::LoadBaseIndexed(int rBase, int r_index, int r_dest,
644 bool all_low_regs = ARM_LOWREG(rBase) && ARM_LOWREG(r_index) && ARM_LOWREG(r_dest);
672 NewLIR4(kThumb2AddRRR, reg_ptr, rBase, r_index,
675 OpRegRegReg(kOpAdd, reg_ptr, rBase, r_index);
699 load = NewLIR3(opcode, r_dest, rBase, r_index);
701 load = NewLIR4(opcode, r_dest, rBase, r_index, scale);
706 LIR* ArmMir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src,
708 bool all_low_regs = ARM_LOWREG(rBase) && ARM_LOWREG(r_index) && ARM_LOWREG(r_src);
736 NewLIR4(kThumb2AddRRR, reg_ptr, rBase, r_index,
739 OpRegRegReg(kOpAdd, reg_ptr, rBase, r_index)
[all...] |
| codegen_arm.h | 32 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
33 LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi,
35 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size);
36 LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
40 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
41 LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi);
42 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size);
43 LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
145 LIR* OpMem(OpKind op, int rBase, int disp);
151 LIR* OpRegMem(OpKind op, int r_dest, int rBase, int offset)
[all...] |
| call_arm.cc | 300 * adr rBase, <table>
304 * ldmia rBase!, {r_key, r_disp}
329 int rBase = AllocTemp();
340 NewLIR3(kThumb2Adr, rBase, 0, reinterpret_cast<uintptr_t>(tab_rec));
347 NewLIR2(kThumb2LdmiaWB, rBase, (1 << r_key) | (1 << r_disp));
|
| int_arm.cc | 497 void ArmMir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset) {
568 LIR* ArmMir2Lir::OpVldm(int rBase, int count) {
569 return NewLIR3(kThumb2Vldms, rBase, fr0, count);
572 LIR* ArmMir2Lir::OpVstm(int rBase, int count) {
573 return NewLIR3(kThumb2Vstms, rBase, fr0, count);
[all...] |
| /dalvik/vm/compiler/codegen/mips/Mips32/ |
| Factory.cpp | 35 static MipsLIR *loadWordDisp(CompilationUnit *cUnit, int rBase, int displacement,
37 static MipsLIR *storeWordDisp(CompilationUnit *cUnit, int rBase,
184 static MipsLIR *loadMultiple(CompilationUnit *cUnit, int rBase, int rMask);
421 static MipsLIR *loadBaseIndexed(CompilationUnit *cUnit, int rBase,
441 first = newLIR3(cUnit, kMipsAddu, tReg , rBase, rIndex);
444 newLIR3(cUnit, kMipsAddu, tReg , rBase, tReg);
483 static MipsLIR *storeBaseIndexed(CompilationUnit *cUnit, int rBase,
504 first = newLIR3(cUnit, kMipsAddu, tReg , rBase, rIndex);
507 newLIR3(cUnit, kMipsAddu, tReg , rBase, tReg);
540 static MipsLIR *loadMultiple(CompilationUnit *cUnit, int rBase, int rMask
[all...] |
| /dalvik/vm/compiler/codegen/mips/ |
| Codegen.h | 80 extern void dvmCompilerFlushRegImpl(CompilationUnit *cUnit, int rBase,
83 extern void dvmCompilerFlushRegWideImpl(CompilationUnit *cUnit, int rBase,
|
| CodegenFactory.cpp | 29 static MipsLIR *loadWordDisp(CompilationUnit *cUnit, int rBase, int displacement,
32 return loadBaseDisp(cUnit, NULL, rBase, displacement, rDest, kWord,
36 static MipsLIR *storeWordDisp(CompilationUnit *cUnit, int rBase,
39 return storeBaseDisp(cUnit, rBase, displacement, rSrc, kWord);
|
| CodegenDriver.cpp | [all...] |
| /dalvik/vm/compiler/codegen/arm/Thumb/ |
| Factory.cpp | 30 static ArmLIR *loadWordDisp(CompilationUnit *cUnit, int rBase, int displacement,
32 static ArmLIR *storeWordDisp(CompilationUnit *cUnit, int rBase,
469 static ArmLIR *loadBaseIndexed(CompilationUnit *cUnit, int rBase,
501 res = newLIR3(cUnit, opcode, rDest, rBase, rNewIndex);
512 static ArmLIR *storeBaseIndexed(CompilationUnit *cUnit, int rBase,
539 res = newLIR3(cUnit, opcode, rSrc, rBase, rNewIndex);
549 static ArmLIR *loadMultiple(CompilationUnit *cUnit, int rBase, int rMask)
553 res = newLIR2(cUnit, kThumbLdmia, rBase, rMask);
562 static ArmLIR *storeMultiple(CompilationUnit *cUnit, int rBase, int rMask)
566 res = newLIR2(cUnit, kThumbStmia, rBase, rMask)
[all...] |
| /dalvik/vm/compiler/codegen/arm/Thumb2/ |
| Factory.cpp | 746 static ArmLIR *loadBaseIndexed(CompilationUnit *cUnit, int rBase,
749 bool allLowRegs = LOWREG(rBase) && LOWREG(rIndex) && LOWREG(rDest);
769 newLIR4(cUnit, kThumb2AddRRR, regPtr, rBase, rIndex,
772 opRegRegReg(cUnit, kOpAdd, regPtr, rBase, rIndex);
799 load = newLIR3(cUnit, opcode, rDest, rBase, rIndex);
801 load = newLIR4(cUnit, opcode, rDest, rBase, rIndex, scale);
810 static ArmLIR *storeBaseIndexed(CompilationUnit *cUnit, int rBase,
813 bool allLowRegs = LOWREG(rBase) && LOWREG(rIndex) && LOWREG(rSrc);
833 newLIR4(cUnit, kThumb2AddRRR, regPtr, rBase, rIndex,
836 opRegRegReg(cUnit, kOpAdd, regPtr, rBase, rIndex)
[all...] |
| /art/compiler/dex/quick/ |
| gen_common.cc | 345 int rBase;
349 rBase = AllocTemp();
351 mirror::ArtMethod::DeclaringClassOffset().Int32Value(), rBase);
366 rBase = TargetReg(kArg0);
367 LockTemp(rBase);
370 rBase);
371 LoadWordDisp(rBase,
373 sizeof(int32_t*) * ssb_index, rBase);
374 // rBase now points at appropriate static storage base (Class*)
377 LIR* branch_over = OpCmpImmBranch(kCondNe, rBase, 0, NULL)
[all...] |
| mir_to_lir.h | 507 LIR* LoadWordDisp(int rBase, int displacement, int r_dest);
514 LIR* StoreWordDisp(int rBase, int displacement, int r_src);
531 virtual LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg) = 0;
532 virtual LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi,
534 virtual LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size) = 0;
535 virtual LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
539 virtual LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) = 0;
540 virtual LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi) = 0;
541 virtual LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size) = 0;
542 virtual LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement
[all...] |
| gen_loadstore.cc | 78 LIR* Mir2Lir::LoadWordDisp(int rBase, int displacement, int r_dest) {
79 return LoadBaseDisp(rBase, displacement, r_dest, kWord,
83 LIR* Mir2Lir::StoreWordDisp(int rBase, int displacement, int r_src) {
84 return StoreBaseDisp(rBase, displacement, r_src, kWord);
|
| /dalvik/vm/compiler/codegen/ |
| Ralloc.h | 221 extern void dvmCompilerFlushRegImpl(CompilationUnit *cUnit, int rBase,
224 extern void dvmCompilerFlushRegWideImpl(CompilationUnit *cUnit, int rBase,
|
| CodegenFactory.cpp | 35 static TGT_LIR *loadWordDisp(CompilationUnit *cUnit, int rBase,
38 return loadBaseDisp(cUnit, NULL, rBase, displacement, rDest, kWord,
42 static TGT_LIR *storeWordDisp(CompilationUnit *cUnit, int rBase,
45 return storeBaseDisp(cUnit, rBase, displacement, rSrc, kWord);
|
| /frameworks/native/opengl/libs/ETC1/ |
| etc1.cpp | 206 int rBase = high >> 27;
209 r1 = convert5To8(rBase);
210 r2 = convertDiff(rBase, high >> 24);
|
| /sdk/emulator/opengl/host/libs/Translator/GLcommon/ |
| etc1.cpp | 206 int rBase = high >> 27;
209 r1 = convert5To8(rBase);
210 r2 = convertDiff(rBase, high >> 24);
|
| /dalvik/vm/compiler/codegen/arm/ |
| CodegenDriver.cpp | [all...] |
