| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeonsi/ |
| si_commands.c | 34 si_pm4_cmd_add(pm4, cp_coher_cntl); /* CP_COHER_CNTL */
35 si_pm4_cmd_add(pm4, 0xffffffff); /* CP_COHER_SIZE */
36 si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE */
37 si_pm4_cmd_add(pm4, 0x0000000A); /* POLL_INTERVAL */
|
| radeonsi_pm4.c | 41 void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw) function
80 si_pm4_cmd_add(state, reg);
84 si_pm4_cmd_add(state, val);
106 si_pm4_cmd_add(state, dw);
122 si_pm4_cmd_add(state, (reg - SI_SH_REG_OFFSET) >> 2);
124 si_pm4_cmd_add(state, offs << 2);
125 si_pm4_cmd_add(state, 0);
|
| radeonsi_pm4.h | 64 void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw);
|
| si_state_draw.c | 477 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (R600_BIG_ENDIAN ?
480 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (R600_BIG_ENDIAN ?
486 si_pm4_cmd_add(pm4, info->instance_count);
496 si_pm4_cmd_add(pm4, (ib->buffer->width0 - ib->offset) /
498 si_pm4_cmd_add(pm4, va);
499 si_pm4_cmd_add(pm4, (va >> 32UL) & 0xFF);
500 si_pm4_cmd_add(pm4, info->count);
501 si_pm4_cmd_add(pm4, V_0287F0_DI_SRC_SEL_DMA);
505 si_pm4_cmd_add(pm4, info->count);
506 si_pm4_cmd_add(pm4, V_0287F0_DI_SRC_SEL_AUTO_INDEX
[all...] |
| si_state.c | [all...] |
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_commands.c | 34 si_pm4_cmd_add(pm4, cp_coher_cntl); /* CP_COHER_CNTL */
35 si_pm4_cmd_add(pm4, 0xffffffff); /* CP_COHER_SIZE */
36 si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE */
37 si_pm4_cmd_add(pm4, 0x0000000A); /* POLL_INTERVAL */
|
| radeonsi_pm4.c | 41 void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw) function
80 si_pm4_cmd_add(state, reg);
84 si_pm4_cmd_add(state, val);
106 si_pm4_cmd_add(state, dw);
122 si_pm4_cmd_add(state, (reg - SI_SH_REG_OFFSET) >> 2);
124 si_pm4_cmd_add(state, offs << 2);
125 si_pm4_cmd_add(state, 0);
|
| radeonsi_pm4.h | 64 void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw);
|
| si_state_draw.c | 477 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_32 | (R600_BIG_ENDIAN ?
480 si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (R600_BIG_ENDIAN ?
486 si_pm4_cmd_add(pm4, info->instance_count);
496 si_pm4_cmd_add(pm4, (ib->buffer->width0 - ib->offset) /
498 si_pm4_cmd_add(pm4, va);
499 si_pm4_cmd_add(pm4, (va >> 32UL) & 0xFF);
500 si_pm4_cmd_add(pm4, info->count);
501 si_pm4_cmd_add(pm4, V_0287F0_DI_SRC_SEL_DMA);
505 si_pm4_cmd_add(pm4, info->count);
506 si_pm4_cmd_add(pm4, V_0287F0_DI_SRC_SEL_AUTO_INDEX
[all...] |
| si_state.c | [all...] |
