| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeonsi/ |
| si_state.c | 55 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
151 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
153 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0);
154 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0);
174 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
189 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
217 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
218 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
219 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
220 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]))
[all...] |
| si_state_draw.c | 67 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
70 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
78 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
79 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
89 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
92 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
170 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
183 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
184 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
185 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control)
[all...] |
| radeonsi_pm4.h | 67 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
|
| radeonsi_pm4.c | 56 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val) function
|
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_state.c | 55 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
151 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
153 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0);
154 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0);
174 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
189 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
217 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
218 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
219 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
220 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]))
[all...] |
| si_state_draw.c | 67 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
70 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
78 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
79 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
89 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
92 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
170 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
183 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
184 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
185 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control)
[all...] |
| radeonsi_pm4.h | 67 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
|
| radeonsi_pm4.c | 56 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val) function
|
