| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 178 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
188 { ISD::SHL, MVT::v4i64, 1 },
189 { ISD::SRL, MVT::v4i64, 1 },
199 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized.
205 { ISD::SDIV, MVT::v4i64, 4*20 },
209 { ISD::UDIV, MVT::v4i64, 4*20 },
303 { ISD::SUB, MVT::v4i64, 4 },
304 { ISD::ADD, MVT::v4i64, 4 },
305 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then
307 // Because we believe v4i64 to be a legal type, we must also include th
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 89 v4i64 = 38, // 4 x i64 enumerator in enum:llvm::MVT::SimpleValueType
220 SimpleTy == MVT::v8i32 || SimpleTy == MVT::v4i64);
287 case v4i64:
327 case v4i64:
398 case v4i64:
518 if (NumElements == 4) return MVT::v4i64;
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 214 DecodeUNPCKHMask(MVT::v4i64, ShuffleMask);
287 DecodeUNPCKLMask(MVT::v4i64, ShuffleMask);
442 // For instruction comments purpose, assume the 256-bit vector is v4i64.
443 DecodeVPERM2X128Mask(MVT::v4i64,
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 156 case MVT::v4i64: return "v4i64";
219 case MVT::v4i64: return VectorType::get(Type::getInt64Ty(Context), 4);
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 215 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
219 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
220 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
407 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 },
|
| ARMISelDAGToDAG.cpp | [all...] |
| ARMISelLowering.cpp | 570 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
571 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 97 case MVT::v4i64: return "MVT::v4i64";
|
