| /external/llvm/test/Transforms/InstCombine/ |
| intrinsics.ll | 9 declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
11 declare i8 @llvm.ctlz.i8(i8, i1) nounwind readnone
171 define i8 @ctlz(i8 %a) {
175 %count = tail call i8 @llvm.ctlz.i8(i8 %and, i1 true) nounwind readnone
177 ; CHECK-LABEL: @ctlz(
184 %lz = tail call i32 @llvm.ctlz.i32(i32 %a, i1 false) nounwind readnone
205 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %x, i1 false)
216 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
225 %ctlz = call i32 @llvm.ctlz.i32(i32 0, i1 true
[all...] |
| sext.ll | 6 declare i32 @llvm.ctlz.i32(i32, i1)
19 %t = call i32 @llvm.ctlz.i32(i32 %x, i1 true)
|
| /external/llvm/test/CodeGen/ARM/ |
| popcnt.ll | 85 %tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0)
93 %tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0)
101 %tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0)
109 %tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0)
117 %tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0)
125 %tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0)
129 declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>, i1) nounwind readnone
130 declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>, i1) nounwind readnone
131 declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone
133 declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) nounwind readnon
[all...] |
| /external/llvm/test/Bitcode/ |
| arm32_neon_vcnt_upgrade.ll | 8 ;CHECK: {{call.*@llvm.ctlz.v4i16\(<4 x i16>.*, i1 false}}
|
| /external/llvm/test/CodeGen/Mips/ |
| mips64instrs.ll | 127 declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
132 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
140 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
|
| /external/llvm/lib/IR/ |
| AutoUpgrade.cpp | 63 // llvm.ctlz.*
66 "llvm.ctlz." + Name.substr(14), F->getParent());
77 if (Name.startswith("ctlz.") && F->arg_size() == 1) {
79 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz,
311 case Intrinsic::ctlz:
321 // Change name from llvm.arm.neon.vclz.* to llvm.ctlz.*
324 "llvm.ctlz." + Name.substr(14)));
|
| /external/llvm/lib/CodeGen/ |
| IntrinsicLowering.cpp | 300 /// LowerCTLZ - Emit the code to lower ctlz of V before the specified
309 ShVal = Builder.CreateLShr(V, ShVal, "ctlz.sh");
310 V = Builder.CreateOr(V, ShVal, "ctlz.step");
399 case Intrinsic::ctlz:
|
| /external/llvm/lib/Transforms/Utils/ |
| IntegerDivision.cpp | 142 Function *CTLZi32 = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz,
199 // ; %tmp0 = tail call i32 @llvm.ctlz.i32(i32 %divisor, i1 true)
200 // ; %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %dividend, i1 true)
|
| /external/chromium_org/native_client_sdk/src/doc/reference/ |
| pnacl-bitcode-abi.rst | 388 * ``llvm.ctlz``
392 The overloaded llvm.ctlz, llvm.cttz, and llvm.ctpop intrinsics are only
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 275 case ISD::CTLZ: return "ctlz";
|
| LegalizeDAG.cpp | [all...] |
| TargetLowering.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 60 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
[all...] |
| LegalizeVectorOps.cpp | 213 case ISD::CTLZ:
|
| LegalizeVectorTypes.cpp | 68 case ISD::CTLZ:
522 case ISD::CTLZ:
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 730 // ctlz.i32(x)>>5 --> zext(x == 0)
733 if ((II->getIntrinsicID() == Intrinsic::ctlz ||
|
| /external/llvm/include/llvm/Target/ |
| TargetSelectionDAG.td | 115 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
352 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
[all...] |
| /external/llvm/lib/Analysis/ |
| ConstantFolding.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.td | [all...] |
| /external/llvm/lib/Target/R600/ |
| AMDILISelLowering.cpp | 145 setOperationAction(ISD::CTLZ, VT, Expand);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 126 setOperationAction(ISD::CTLZ, MVT::i8, Expand);
127 setOperationAction(ISD::CTLZ, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.td | 740 [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR>,
745 [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR>,
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 158 setOperationAction(ISD::CTLZ, VT, Expand);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.td | [all...] |
