| /external/llvm/test/CodeGen/Mips/ |
| global-pointer-reg.ll | 14 ; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)
|
| mips64ext.ll | 5 ; CHECK: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, 2
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| sub1.ll | 10 ; 16: addiu ${{[0-9]+}}, -{{[0-9]+}}
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| helloworld.ll | 30 ; PE: addiu $[[T2:[0-9]+]], $pc, %lo(_gp_disp)
34 ; C1: addiu ${{[0-9]+}}, %lo($.str)
44 ; ST1: addiu ${{[0-9]+}}, %lo($.str)
|
| internalfunc.ll | 10 ; CHECK: addiu $25, $[[R0]], %lo(f2)
29 ; CHECK: addiu ${{[0-9]+}}, $[[R2]], %lo(sf2)
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| longbranch.ll | 10 ; O32: addiu $1, $1, {{[0-9]+}}
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| alloca16.ll | 71 ; 16: addiu $sp, -16
73 ; 16: addiu $sp, 16
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| mips16_32_5.ll | 57 ; 16: addiu $2, $zero, 0
69 ; 32: addiu $2, $zero, 0
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| mips16_32_6.ll | 63 ; 16: addiu $2, $zero, 0
75 ; 32: addiu $2, $zero, 0
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| /external/llvm/test/MC/Mips/ |
| lea_64.ll | 10 ; CHECK-NOT: addiu {{[0-9,a-f]+}}, {{[0-9,a-f]+}}, {{[0-9]+}}
|
| /external/pixman/pixman/ |
| pixman-mips-memcpy-asm.S | 148 addiu a0, a0, 64 /* adding 64 to dest */
151 addiu a1, a1, 64 /* adding 64 to src */
171 addiu a1, a1, 32
181 addiu a0, a0, 32
192 addiu a1, a1, 4
193 addiu a0, a0, 4
203 addiu a1, a1, 1
204 addiu a0, a0, 1
311 addiu a0, a0, 64 /* adding 64 to dest */
314 addiu a1, a1, 64 /* adding 64 to src *
[all...] |
| /system/core/libcutils/tests/memset_mips/ |
| memset_omips.S | 64 addiu a0, 8 # Handle 2 words pr. iteration
74 addiu a0, 4
80 addiu a0, 1
|
| memset_cmips.S | 122 addiu a0,a0,64
161 addiu a0,a0,64
195 addiu a0,a0,32
205 addiu a0,a0,4
210 .Llast4l:addiu a0,a0,1
|
| /art/runtime/arch/mips/ |
| portable_entrypoints_mips.S | 27 addiu $sp, $sp, -64
60 addiu $sp, $sp, 64 # pop frame
|
| quick_entrypoints_mips.S | 33 addiu $sp, $sp, -64
67 addiu $sp, $sp, -64
93 addiu $sp, $sp, 64
101 addiu $sp, $sp, 64
111 addiu $sp, $sp, -64
146 addiu $sp, $sp, 64 # pop frame
368 addiu $sp, $sp, -32 # make space for extra args
374 addiu $sp, $sp, 32 # release out args
412 addiu $sp, $sp, -16 # spill s0, s1, fp, ra
425 addiu $s0, $zero, SUSPEND_CHECK_INTERVAL # reset s0 to suspend check interva
[all...] |
| /external/kernel-headers/original/asm-mips/ |
| div64.h | 44 " addiu %4, %4, -1\n\t" \
46 "addiu %2, %2, 1\n" \
|
| /external/llvm/lib/Target/Mips/ |
| MipsJITInfo.cpp | 64 // addiu t0, t0, low 16 bit of the NewAddr
109 "addiu $sp, $sp, -64\n"
129 "addiu $a0, $t8, -16\n"
142 "addiu $sp, $sp, 64\n"
145 "addiu $t8, $t8, -16\n"
172 // addiu $t9, $t9, %lo(NewVal)
222 // addiu $t9, $t9, %lo(EmittedAddr)
|
| MipsSEISelDAGToDAG.cpp | 73 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
74 if ((MI.getOpcode() == Mips::ADDiu) &&
150 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
153 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
164 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
169 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
180 // 1. addiu $2, $2, %lo(_gp_disp)
191 // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
284 // addiu $2, $2, %lo($CPI1_0)
383 // instructions (ADDiu, ORI and SLL) in that it does not have a registe
[all...] |
| /external/jpeg/ |
| mips_idct_le.S | 63 addiu $sp, $sp, -32 # reserve stack space for s0-s7
74 addiu $t9, $a0, 16 # end address
120 addiu $a0, $a0, 4
123 addiu $a1, $a1, 4
228 addiu $a0, $a0, 4
229 addiu $a1, $a1, 4
262 addiu $a2, $a2, 4
275 addiu $sp, $sp, 32
307 addiu $sp, $sp, -48 # reserve stack space for s0-s8
322 addiu $t9, $a0, 128 # end addres
[all...] |
| /bionic/libc/kernel/arch-mips/asm/ |
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
| /bionic/libc/private/ |
| bionic_atomic_mips.h | 79 " addiu %[status], %[prev], 1 \n"
94 " addiu %[status], %[prev], -1 \n"
|
| /development/ndk/platforms/android-9/arch-mips/include/asm/ |
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-mips.cc | 150 COMPARE(addiu(a0, a1, 0x0),
151 "24a40000 addiu a0, a1, 0");
152 COMPARE(addiu(s0, s1, 32767),
153 "26307fff addiu s0, s1, 32767");
154 COMPARE(addiu(t2, t3, -32768),
155 "256a8000 addiu t2, t3, -32768");
156 COMPARE(addiu(v0, v1, -1),
157 "2462ffff addiu v0, v1, -1");
|
| /external/v8/test/cctest/ |
| test-disasm-mips.cc | 160 COMPARE(addiu(a0, a1, 0x0),
161 "24a40000 addiu a0, a1, 0");
162 COMPARE(addiu(s0, s1, 32767),
163 "26307fff addiu s0, s1, 32767");
164 COMPARE(addiu(t2, t3, -32768),
165 "256a8000 addiu t2, t3, -32768");
166 COMPARE(addiu(v0, v1, -1),
167 "2462ffff addiu v0, v1, -1");
|
| /prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/asm/ |
| div64.h | 25 #define do_div64_32(res, high, low, base) ({ unsigned long __quot32, __mod32; unsigned long __cf, __tmp, __tmp2, __i; __asm__(".set push\n\t" ".set noat\n\t" ".set noreorder\n\t" "move %2, $0\n\t" "move %3, $0\n\t" "b 1f\n\t" " li %4, 0x21\n" "0:\n\t" "sll $1, %0, 0x1\n\t" "srl %3, %0, 0x1f\n\t" "or %0, $1, %5\n\t" "sll %1, %1, 0x1\n\t" "sll %2, %2, 0x1\n" "1:\n\t" "bnez %3, 2f\n\t" " sltu %5, %0, %z6\n\t" "bnez %5, 3f\n" "2:\n\t" " addiu %4, %4, -1\n\t" "subu %0, %0, %z6\n\t" "addiu %2, %2, 1\n" "3:\n\t" "bnez %4, 0b\n\t" " srl %5, %1, 0x1f\n\t" ".set pop" : "=&r" (__mod32), "=&r" (__tmp), "=&r" (__quot32), "=&r" (__cf), "=&r" (__i), "=&r" (__tmp2) : "Jr" (base), "0" (high), "1" (low)); (res) = __quot32; __mod32; })
|
