| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/sys/ |
| gmon_out.h | 74 char self_pc[sizeof (char *)]; /* address within callee's body */
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/sys/ |
| gmon_out.h | 74 char self_pc[sizeof (char *)]; /* address within callee's body */
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/sys/ |
| gmon_out.h | 74 char self_pc[sizeof (char *)]; /* address within callee's body */
|
| /external/llvm/include/llvm/IR/ |
| IRBuilder.h | 512 InvokeInst *CreateInvoke(Value *Callee, BasicBlock *NormalDest,
514 return Insert(InvokeInst::Create(Callee, NormalDest, UnwindDest,
518 InvokeInst *CreateInvoke(Value *Callee, BasicBlock *NormalDest,
521 return Insert(InvokeInst::Create(Callee, NormalDest, UnwindDest, Arg1),
524 InvokeInst *CreateInvoke3(Value *Callee, BasicBlock *NormalDest,
529 return Insert(InvokeInst::Create(Callee, NormalDest, UnwindDest, Args),
533 InvokeInst *CreateInvoke(Value *Callee, BasicBlock *NormalDest,
536 return Insert(InvokeInst::Create(Callee, NormalDest, UnwindDest, Args),
[all...] |
| /external/llvm/lib/Analysis/IPA/ |
| InlineCost.cpp | 63 /// Number of bytes allocated statically by the callee.
138 Function &Callee, int Threshold)
139 : TD(TD), TTI(TTI), F(Callee), Threshold(Threshold), Cost(0),
761 Value *Callee = CS.getCalledValue();
769 Function *F = dyn_cast_or_null<Function>(SimplifiedValues.lookup(Callee));
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 357 SDValue Callee) const {
390 SDValue Callee = CLI.Callee;
404 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Callee))
407 Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, MVT::i32);
412 // varargs if the callee is undefined.
429 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
551 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
557 Callee =
560 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
[all...] |
| HexagonISelLowering.h | 84 IsEligibleForTailCallOptimization(SDValue Callee,
125 SDValue Callee) const;
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 312 // Add callee saved registers to move list.
641 /// emitPrologue - Push callee-saved registers onto the stack, which
681 // Add RETADDR move area to callee saved frame size.
707 // applies to tail call optimized functions where the callee argument stack
741 // Callee-saved registers are pushed on stack before the stack
802 // Skip the callee-saved push instructions.
814 // Mark callee-saved push instruction.
826 // Realign stack after we pushed callee-saved registers (so that we'll be
830 // vector callee-saved (xmm) registers may be saved w/o proper
849 // the callee has more arguments then the caller
[all...] |
| /art/compiler/ |
| compiled_method.h | 160 // For quick code, a bit mask describing spilled GPR callee-save registers.
162 // For quick code, a bit mask describing spilled FPR callee-save registers.
|
| /art/compiler/jni/quick/arm/ |
| calling_convention_arm.cc | 134 // Compute spill mask to agree with callee saves initialized in the constructor
145 // Method*, LR and callee save area size, local reference segment state
|
| /art/compiler/jni/quick/mips/ |
| calling_convention_mips.cc | 137 // Compute spill mask to agree with callee saves initialized in the constructor
149 // Method*, LR and callee save area size, local reference segment state
|
| /external/chromium_org/third_party/tcmalloc/chromium/src/ |
| stacktrace_arm-inl.h | 47 // mode) or r7 (THUMB mode). A callee only saves the frame pointer of its
50 // still in the designated register or saved on stack along with other callee
|
| /external/chromium_org/third_party/tcmalloc/vendor/src/ |
| stacktrace_arm-inl.h | 47 // mode) or r7 (THUMB mode). A callee only saves the frame pointer of its
50 // still in the designated register or saved on stack along with other callee
|
| /external/chromium_org/v8/src/arm/ |
| frames-arm.h | 62 // Callee-saved registers preserved when switching from C to JavaScript
85 // Double registers d8 to d15 are callee-saved.
|
| /external/chromium_org/v8/test/cctest/ |
| test-code-stubs-arm.cc | 61 // Save callee save registers.
121 // Restore callee save registers.
|
| /external/chromium_org/v8/test/mjsunit/ |
| arguments-opt.js | 89 assertEquals(A, A('callee'));
119 assertEquals(A, A(O('callee')));
|
| arguments.js | 113 return arguments.callee(arguments[0] - 1) + arguments[0];
163 assertEquals("function", typeof a.callee);
|
| /external/llvm/include/llvm/Support/ |
| Recycler.h | 75 // If this fails, either the callee has lost track of some allocation,
76 // or the callee isn't tracking allocations and should just call
|
| /external/llvm/lib/CodeGen/ |
| IntrinsicLowering.cpp | 344 const Function *Callee = CI->getCalledFunction();
345 assert(Callee && "Cannot lower an indirect call!");
348 switch (Callee->getIntrinsicID()) {
351 Callee->getName() + "'!");
354 Callee->getName()+"'!");
419 << (Callee->getIntrinsicID() == Intrinsic::stacksave ?
422 if (Callee->getIntrinsicID() == Intrinsic::stacksave)
430 << (Callee->getIntrinsicID() == Intrinsic::returnaddress ?
|
| /external/llvm/lib/ExecutionEngine/ |
| RTDyldMemoryManager.cpp | 95 // callee's(eg. tools/lli) one, to invoke wrong duplicated ctors
96 // (and register wrong callee's dtors with atexit(3)).
|
| /external/llvm/lib/IR/ |
| IRBuilder.cpp | 55 static CallInst *createCallHelper(Value *Callee, ArrayRef<Value *> Ops,
57 CallInst *CI = CallInst::Create(Callee, Ops, "");
|
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelLowering.cpp | 419 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
432 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(CLI.Callee)) {
454 dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
467 SDValue JumpTarget = Callee;
469 // T9 should contain the address of the callee function if
474 RegsToPass.push_front(std::make_pair(V0Reg, Callee));
478 RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee));
484 InternalLinkage, CLI, Callee, Chain);
|
| Mips16RegisterInfo.cpp | 101 // 3. Locations for callee-saved registers.
128 // incoming argument, callee-saved register location or local variable.
|
| MipsSERegisterInfo.cpp | 88 // 3. Locations for callee-saved registers.
105 // incoming argument, callee-saved register location or local variable.
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXRegisterInfo.cpp | 80 /// NVPTX Callee Saved Registers
87 // NVPTX Callee Saved Reg Classes
|
