| /external/mesa3d/src/gallium/drivers/llvmpipe/ |
| lp_test_conv.c | 66 double cycles,
71 fprintf(fp, "%.1f\t", cycles / MAX2(src_type.length, dst_type.length));
163 int64_t cycles[LP_TEST_NUM_SAMPLES]; local
246 cycles[i] = end_counter - start_counter;
299 sum += cycles[i];
300 sum2 += cycles[i]*cycles[i];
309 if(fabs(cycles[i] - avg) <= 4.0*std) {
310 sum += cycles[i];
|
| /external/netperf/ |
| netcpu_pstatnew.c | 217 /* calculate our sanity check on cycles */
230 accounting for interrupt cycles, whereby the cycles do not get
233 Some cycles go missing.
237 idle cycles is sufficiently accurate. So, while we will still do
238 math with user, kernel and interrupt cycles, we will only
240 total cycles. I am told that a "future release" of HP-UX will
243 /* calculate what the sum of CPU cycles _SHOULD_ be */
305 all the "missing" cycles to it. raj 2005/09/14 */
|
| /external/llvm/lib/Target/X86/ |
| X86SchedHaswell.td | 61 // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
62 // cycles after the memory operand.
76 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the
99 // The complex ones can only execute on port 1, and they require two cycles on
116 defm : HWWriteResPair<WriteFDiv, HWPort0, 12>; // 10-14 cycles.
|
| X86SchedSandyBridge.td | 56 // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
57 // cycles after the memory operand.
71 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the
94 // The complex ones can only execute on port 1, and they require two cycles on
111 defm : SBWriteResPair<WriteFDiv, SBPort0, 12>; // 10-14 cycles.
|
| /external/oprofile/events/alpha/ev67/ |
| events | 3 event:0x00 counters:0 um:zero minimum:500 name:CYCLES : Total cycles
4 event:0x01 counters:1 um:zero minimum:500 name:DELAYED_CYCLES : Cycles of delayed retire pointer advance
|
| /external/oprofile/events/arm/mpcore/ |
| events | 4 event:0x01 counters:0,1 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled
5 event:0x02 counters:0,1 um:zero minimum:500 name:CYCLES_DATA_STALL : cycles stall occurs for due to data dependency
25 event:0xff counters:0,1 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter
|
| /external/oprofile/events/i386/athlon/ |
| events | 3 event:0x76 counters:0,1,2,3 um:zero minimum:3000 name:CPU_CLK_UNHALTED : Cycles outside of halt state
24 event:0xcd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED : Interrupts masked cycles (IF=0)
25 event:0xce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_PENDING : Interrupts masked while pending cycles (INTR while IF=0)
|
| /external/qemu/docs/ |
| ANDROID-TRACING.TXT | 44 - the number of virtual CPU cycles / instruction is returned by get_insn_ticks_arm()
46 variable cycles due to operand sizes (e.g. multiplications instructions).
59 cycles. This just increments a global uint64_t counter.
|
| /external/dropbear/libtommath/demo/ |
| timing.c | 122 printf("Adding\t\t%4d-bit => %9llu/sec, %9llu cycles\n",
144 printf("Subtracting\t\t%4d-bit => %9llu/sec, %9llu cycles\n",
175 printf("Multiplying\t%4d-bit => %9llu/sec, %9llu cycles\n",
195 printf("Squaring\t%4d-bit => %9llu/sec, %9llu cycles\n",
272 printf("Exponentiating\t%4d-bit => %9llu/sec, %9llu cycles\n",
308 printf("Inverting mod\t%4d-bit => %9llu/sec, %9llu cycles\n",
|
| /external/chromium/chrome/browser/ui/gtk/ |
| hover_controller_gtk.cc | 39 void HoverControllerGtk::StartThrobbing(int cycles) {
40 throb_animation_.StartThrobbing(cycles);
|
| /external/chromium-trace/trace-viewer/src/tracing/importer/linux_perf/ |
| bus_parser.js | 38 'w_bytes=(\\d+) cycles=(\\d+) ns=(\\d+)');
45 var cycles = parseInt(event[5]);
|
| /external/chromium_org/chrome/browser/ui/gtk/ |
| hover_controller_gtk.cc | 40 void HoverControllerGtk::StartThrobbing(int cycles) {
41 throb_animation_.StartThrobbing(cycles);
|
| /external/chromium_org/net/proxy/ |
| dhcp_proxy_script_fetcher_factory.h | 41 // reference to |url_request_context|. Be careful not to create cycles
42 // between the fetcher and the context; you can break such cycles by calling
|
| /external/chromium_org/sync/sessions/ |
| test_util.h | 64 // Works with poll cycles.
70 // Works with normal cycles.
|
| /external/chromium_org/third_party/mesa/src/src/mesa/math/ |
| m_debug_xform.c | 48 /* Overhead of profiling counter in cycles. Automatically adjusted to
169 int mtype, unsigned long *cycles )
179 (void) cycles;
246 BEGIN_RACE( *cycles );
248 END_RACE( *cycles );
295 printf("counter overhead: %lu cycles\n\n", counter_overhead );
314 unsigned long *cycles = &(benchmark_tab[psize-1][mtype]); local
316 if ( test_transform_function( func, psize, mtype, cycles ) == 0 ) {
|
| /external/llvm/include/llvm/MC/ |
| MCInstrItineraries.h | 26 /// the execution of an instruction. Cycles represents the number of
30 /// cycles should elapse from the start of this stage to the start of
41 /// consecuative cycles and that the next stage starts one cycle
65 unsigned Cycles_; ///< Length of stage in machine cycles
67 int NextCycles_; ///< Number of machine cycles to next stage
70 /// getCycles - returns the number of cycles the stage is occupied
84 /// getNextCycles - returns the number of cycles from the start of
115 const unsigned *OperandCycles; ///< Array of operand cycles selected
|
| /external/llvm/include/llvm/Target/ |
| TargetItinerary.td | 44 // the execution of an instruction. Cycles represents the number of
48 // cycles should elapse from the start of this stage to the start of
53 // InstrStage<1, [FU_x, FU_y]> - TimeInc defaults to Cycles
57 class InstrStage<int cycles, list<FuncUnit> units,
60 int Cycles = cycles; // length of stage in machine cycles
62 int TimeInc = timeinc; // cycles till start of next stage
|
| /external/mesa3d/src/mesa/math/ |
| m_debug_xform.c | 48 /* Overhead of profiling counter in cycles. Automatically adjusted to
169 int mtype, unsigned long *cycles )
179 (void) cycles;
246 BEGIN_RACE( *cycles );
248 END_RACE( *cycles );
295 printf("counter overhead: %lu cycles\n\n", counter_overhead );
314 unsigned long *cycles = &(benchmark_tab[psize-1][mtype]); local
316 if ( test_transform_function( func, psize, mtype, cycles ) == 0 ) {
|
| /external/oprofile/events/i386/core_2/ |
| events | 5 event:0x3c counters:0,1 um:nonhlt minimum:6000 name:CPU_CLK_UNHALTED : Clock cycles when not halted
19 event:0x09 counters:0,1 um:memory_dis minimum:1000 name:MEMORY_DISAMBIGUATION : Memory disambiguation reset cycles.
25 event:0x14 counters:0,1 um:zero minimum:1000 name:CYCLES_DIV_BUSY : cycles divider is busy
26 event:0x18 counters:0,1 um:zero minimum:1000 name:IDLE_DURING_DIV : cycles divider is busy and all other execution units are idle.
28 event:0x21 counters:0,1 um:core minimum:500 name:L2_ADS : Cycles the L2 address bus is in use.
29 event:0x23 counters:0,1 um:core minimum:500 name:L2_DBUS_BUSY_RD : Cycles the L2 transfers data to the core.
39 event:0x32 counters:0,1 um:core minimum:500 name:L2_NO_REQ : Cycles no L2 cache requests are pending
59 event:0x62 counters:0,1 um:bus_agents minimum:500 name:BUS_DRDY_CLOCKS : Bus cycles when data is sent on the bus
60 event:0x63 counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_LOCK_CLOCKS : Bus cycles when a LOCK signal is asserted
61 event:0x64 counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_DATA_RCV : Bus cycles while processor receives dat
[all...] |
| unit_masks | 24 0x0 Unhalted core cycles
25 0x1 Unhalted bus cycles
26 0x2 Unhalted bus cycles of this core while the other core is halted
59 0x01 SB_DRAIN_CYCLES Cycles while stores are blocked due to store buffer drain.
60 0x02 ORDER Cycles while store is waiting for a preceding store to be globally observed.
68 0x01 RESET Memory disambiguation reset cycles.
72 0x02 CYCLES Duration of page-walks in core cycles.
|
| /external/oprofile/events/mips/20K/ |
| events | 6 event:0x0 counters:0 um:zero minimum:500 name:CYCLES : CPU cycles
|
| /external/oprofile/events/ppc64/power6/ |
| events | 19 event:0X001 counters:3 um:zero minimum:10000 name:CYCLES : Processor Cycles
22 event:0X002 counters:1 um:zero minimum:10000 name:CYCLES_RND_SMPL : Processor Cycles with random sampling
26 event:0X0010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles
29 event:0X0013 counters:3 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_utilization) Processor cycles
32 event:0X0020 counters:0 um:zero minimum:1000 name:PM_THRD_ONE_RUN_CYC_GRP2 : (Group 2 pm_utilization_capacity) One of the threads in run cycles
33 event:0X0021 counters:1 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_utilization_capacity) Processor cycles
98 event:0X00D0 counters:0 um:zero minimum:1000 name:PM_LD_MISS_L1_CYC_GRP13 : (Group 13 pm_dlatencies) L1 data load miss cycles
100 event:0X00D2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP13 : (Group 13 pm_dlatencies) Processor cycles
106 event:0X00E2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP14 : (Group 14 pm_dlatencies2) Processor cycles
[all...] |
| /development/samples/Spinner/ |
| _index.html | 16 management of state across invocations and power cycles.
|
| /external/chromium_org/chrome/browser/sync/test/integration/performance/ |
| sync_timing_helper.h | 33 // respective sync cycles.
|
| /external/chromium_org/third_party/WebKit/ManualTests/ |
| tabbing-input-google.html | 11 2) Hit tab until focus cycles through the text fields in the page, and comes back to the Google field.<br>
|
