| /external/oprofile/events/ppc64/970/ |
| events | 14 event:0X001 counters:1 um:zero minimum:10000 name:CYCLES : Processor Cycles
18 event:0X010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_slice0) Run cycles
19 event:0X011 counters:1 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles
23 event:0X015 counters:5 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles
28 event:0X020 counters:0 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles
29 event:0X021 counters:1 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles
39 event:0X031 counters:1 um:zero minimum:10000 name:PM_CYC_GRP3 : (Group 3 pm_basic) Processor cycles
50 event:0X042 counters:2 um:zero minimum:10000 name:PM_CYC_GRP4 : (Group 4 pm_lsu) Processor cycles
62 event:0X054 counters:4 um:zero minimum:10000 name:PM_CYC_GRP5 : (Group 5 pm_fpu1) Processor cycles
[all...] |
| /external/oprofile/events/mips/1004K/ |
| events | 14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
36 event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU
42 event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 34K family microarchitecture)
43 event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles
55 event:0x24 counters:0 um:zero minimum:500 name:INTERVENTION_STALLS : 36-0 Cache coherence intervention processing stall cycles
58 # Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
60 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
62 event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipelin
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMScheduleA9.td | 82 // No operand cycles
203 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
347 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
469 // Extra latency cycles since wbck is 2 cycles
478 // Extra latency cycles since wbck is 2 cycles
488 // Extra latency cycles since wbck is 4 cycles
497 // Extra latency cycles since wbck is 4 cycle
[all...] |
| /external/chromium_org/ppapi/shared_impl/ |
| unittest_utils.h | 14 // two PP_Var graphs being compared is identical, including graphs with cycles.
|
| /external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/org.apache.ant_1.7.1.v20090120-1145/etc/ |
| jdepend-frames.xsl | 57 <!-- create the overview-cycles.html at the root -->
58 <redirect:write file="{$output.dir}/overview-cycles.html">
59 <xsl:apply-templates select="." mode="cycles.details"/>
62 <!-- create the overview-cycles.html at the root -->
72 <!-- create the all-cycles.html at the root -->
73 <redirect:write file="{$output.dir}/all-cycles.html">
74 <xsl:apply-templates select="Cycles" mode="all.cycles"/>
87 <frame src="all-cycles.html" name="classListFrame"/>
166 [<a href="overview-cycles.html">cycles</a>
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCSchedule.h | 38 // their resource some fixed number of cycles after dispatch (e.g. for
49 /// scheduling class for the specified number of cycles.
52 unsigned Cycles;
55 return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
59 /// Specify the latency in cpu cycles for a particular scheduling class and def
65 int Cycles;
69 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
73 /// Specify the number of cycles allowed after instruction issue before
[all...] |
| /external/llvm/test/Analysis/BasicAA/ |
| unreachable-block.ll | 3 ; BasicAA shouldn't infinitely recurse on the use-def cycles in
|
| /external/oprofile/events/alpha/ev4/ |
| events | 8 event:0x0a counters:0 um:zero minimum:4096 name:CYCLES : Total cycles
9 event:0x0b counters:0 um:zero minimum:4096 name:PAL_MODE : Cycles while in PALcode environment
13 event:0x12 counters:0 um:zero minimum:256 name:DUAL_ISSUE_CYCLES : Cycles of dual issue
|
| /external/oprofile/events/i386/ppro/ |
| events | 8 event:0x48 counters:0,1 um:zero minimum:500 name:DCU_MISS_OUTSTANDING : number of cycles while DCU miss outstanding
12 event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is stalled
13 event:0x87 counters:0,1 um:zero minimum:500 name:ILD_STALL : cycles instruction length decoder is stalled
23 event:0x22 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY : number of cycles data bus was busy
24 event:0x23 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY_RD : cycles data bus was busy in xfer from L2 to CPU
40 event:0x64 counters:0,1 um:zero minimum:500 name:BUS_DATA_RCV : bus cycles this processor is receiving data
41 event:0x61 counters:0,1 um:zero minimum:500 name:BUS_BNR_DRV : bus cycles this processor is driving BNR pin
42 event:0x7a counters:0,1 um:zero minimum:500 name:BUS_HIT_DRV : bus cycles this processor is driving HIT pin
43 event:0x7b counters:0,1 um:zero minimum:500 name:BUS_HITM_DRV : bus cycles this processor is driving HITM pin
44 event:0x7e counters:0,1 um:zero minimum:500 name:BUS_SNOOP_STALL : cycles during bus snoop stal
[all...] |
| /external/oprofile/events/ia64/itanium/ |
| events | 2 event:0x12 counters:0,1,2,3 um:zero minimum:500 name:CPU_CYCLES : CPU Cycles
|
| /external/oprofile/events/x86-64/family15h/ |
| events | 15 event:0x76 counters:0,1,2 um:zero minimum:50000 name:CPU_CLK_UNHALTED : Cycles outside of halt state
|
| /external/valgrind/main/none/tests/ppc32/ |
| bug139050-ppc32.c | 30 /* implausible that machine has been up less than 4G cycles */
|
| /external/oprofile/events/mips/74K/ |
| events | 14 event:0x0 counters:0,1,2,3 um:zero minimum:500 name:CYCLES : 0-0 Cycles
21 event:0x3 counters:0,2 um:zero minimum:500 name:REDIRECT_STALLS : 3-0 Stall cycles due to register indirect jumps (including non-predicted JR $31), ERET/WAIT instructions, and IFU determined exception
25 event:0x7 counters:0,2 um:zero minimum:500 name:ICACHE_MISS_STALLS : 7-0 Instruction cache miss stall cycles
26 event:0x8 counters:0,2 um:zero minimum:500 name:UNCACHED_IFETCH_STALLS : 8-0 Uncached instruction fetch stall cycles
29 event:0xb counters:0,2 um:zero minimum:500 name:IFU_IDU_MISS_PRED_UPSTREAM_CYCLES : 11-0 Cycles IFU-IDU gate is closed (to prevent upstream from getting ahead) due to mispredicted branch
30 event:0xc counters:0,2 um:zero minimum:500 name:IFU_IDU_CLOGED_DOWNSTREAM_CYCLES : 12-0 Cycles IFU-IDU gate is closed (waiting for downstream to unclog) due to MTC0/MFC0 sequence in pipe, EHB, or blocked DD, DR, or DS
31 event:0xd counters:0,2 um:zero minimum:500 name:DDQ0_FULL_DR_STALLS : 13-0 DR stage stall cycles due to DDQ0 (ALU out-of-order dispatch queue) full
32 event:0xe counters:0,2 um:zero minimum:500 name:ALCB_FULL_DR_STALLS : 14-0 DR stage stall cycles due to ALCB (ALU completion buffers) full
33 event:0xf counters:0,2 um:zero minimum:500 name:CLDQ_FULL_DR_STALLS : 15-0 DR stage stall cycles due to CLDQ (data comming back from FPU) ful
[all...] |
| /external/oprofile/events/ppc64/ibm-compat-v1/ |
| events | 18 event:0X001 counters:2 um:zero minimum:10000 name:CYCLES : Processor Cycles
22 event:0X0010 counters:0 um:zero minimum:1000 name:PM_THRD_ONE_RUN_CYC_GRP1 : (Group 1 pm_compat_utilization1) At least one thread in run cycles
23 event:0X0011 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_compat_utilization1) Run cycles
24 event:0X0012 counters:2 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_compat_utilization1) Processor cycles
29 event:0X0021 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP2 : (Group 2 pm_compat_utilization2) Run cycles
30 event:0X0022 counters:2 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_compat_utilization2) Processor cycles
65 event:0X0081 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP8 : (Group 8 pm_compat_cpi_1plus_ppc) Run cycles
67 event:0X0083 counters:3 um:zero minimum:1000 name:PM_1PLUS_PPC_DISP_GRP8 : (Group 8 pm_compat_cpi_1plus_ppc) Cycles at least one instruction dispatched
73 event:0X0093 counters:3 um:zero minimum:10000 name:PM_CYC_GRP9 : (Group 9 pm_compat_misc_events1) Processor cycles
[all...] |
| /external/oprofile/events/i386/westmere/ |
| unit_masks | 19 0x01 cycles_div_busy Cycles the divider is busy
58 0x01 l1d_l2 Cycles L1D and L2 locked
59 0x02 l1d Cycles L1D locked
61 0x00 thread_p Cycles when thread is not halted (programmable counter)
62 0x01 ref_p Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)
66 0x04 walk_cycles DTLB load miss page walk cycles
73 0x04 walk_cycles DTLB miss page walk cycles
95 0x01 lcp Length Change Prefix stall cycles
96 0x02 mru Stall cycles due to BPU MRU bypass
97 0x04 iq_full Instruction Queue full stall cycles
[all...] |
| /external/oprofile/events/mips/34K/ |
| events | 14 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
36 event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU
42 event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 34K family microarchitecture)
43 event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles
57 # Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
59 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
61 event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline
62 event:0x28 counters:0 um:zero minimum:500 name:UNCACHED_STALLS : 40-0 Uncached stall cycles
[all...] |
| /external/oprofile/events/ppc64/power5+/ |
| events | 14 event:0X001 counters:3 um:zero minimum:10000 name:CYCLES : Processor Cycles using continuous sampling
17 event:0X002 counters:2 um:zero minimum:10000 name:CYCLES_RND_SMPL : Processor Cycles with random sampling
21 event:0X010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles
24 event:0X013 counters:3 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_utilization) Processor cycles
26 event:0X015 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles
30 event:0X021 counters:1 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP2 : (Group 2 pm_completion) Cycles GCT empty
32 event:0X023 counters:3 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_completion) Processor cycles
34 event:0X025 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP2 : (Group 2 pm_completion) Run cycles
39 event:0X032 counters:2 um:zero minimum:1000 name:PM_GRP_DISP_BLK_SB_CYC_GRP3 : (Group 3 pm_group_dispatch) Cycles group dispatch blocked by scoreboar
[all...] |
| /external/chromium_org/third_party/openssl/openssl/crypto/ripemd/ |
| README | 5 off the pace since I only get 1050 cycles, while the best is 1013.
6 I have a few ideas for how to get another 20 or so cycles, but at
|
| /external/openssl/crypto/ripemd/ |
| README | 5 off the pace since I only get 1050 cycles, while the best is 1013.
6 I have a few ideas for how to get another 20 or so cycles, but at
|
| /external/oprofile/events/alpha/ev6/ |
| events | 3 event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Total cycles
|
| /external/oprofile/events/i386/arch_perfmon/ |
| events | 4 event:0x3c counters:cpuid um:zero minimum:6000 filter:0 name:CPU_CLK_UNHALTED : Clock cycles when not halted
5 event:0x3c counters:cpuid um:one minimum:6000 filter:2 name:UNHALTED_REFERENCE_CYCLES : Unhalted reference cycles
|
| /external/oprofile/events/mips/vr5500/ |
| events | 6 event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor clock cycles
|
| /external/oprofile/events/ppc64/pa6t/ |
| events | 9 event:0x1 counters:0 um:zero minimum:10000 name:CYCLES : Processor Cycles
10 event:0x3 counters:3 um:zero minimum:10000 name:ISS_CYCLES : Processor Cycles with instructions issued
14 event:0x10 counters:0 um:zero minimum:10000 name:GRP1_CYCLES : Processor Cycles
22 event:0x20 counters:0 um:zero minimum:10000 name:GRP2_CYCLES : Processor Cycles
30 event:0x30 counters:0 um:zero minimum:10000 name:GRP3_CYCLES : Processor Cycles
38 event:0x40 counters:0 um:zero minimum:10000 name:GRP4_CYCLES : Processor Cycles
46 event:0x50 counters:0 um:zero minimum:10000 name:GRP5_CYCLES : Processor Cycles
|
| /external/valgrind/main/memcheck/tests/ |
| leak-cycle.c | 43 /* two simple cycles */
62 /* two linked cycles */
|
| /external/oprofile/events/arm/xscale1/ |
| events | 4 event:0x01 counters:1,2 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled
5 event:0x02 counters:1,2 um:zero minimum:500 name:CYCLES_DATA_STALL : cycles stall occurs for due to data dependency
11 event:0x08 counters:1,2 um:zero minimum:500 name:CYCLES_DCACHE_FULL_STALL : cycles in stall due to full dcache
18 event:0x11 counters:1,2 um:zero minimum:500 name:BCU_FULL : number of cycles the BCUs request queue is full
23 event:0xfe counters:0 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter
|
