| /external/oprofile/events/i386/p4-ht/ |
| events | 18 event:0x1c counters:3 um:machine_clear minimum:6000 name:MACHINE_CLEAR : cycles with entire machine pipeline cleared
|
| /external/oprofile/events/mips/loongson2/ |
| events | 3 event:0x00 counters:0 um:zero minimum:10000 name:CPU_CLK_UNHALTED : Cycles outside of haltstate
|
| /external/skia/src/pdf/ |
| SkPDFPage.h | 77 * have both parent and children links, creating reference cycles, so
|
| /frameworks/native/cmds/flatland/ |
| README.txt | 16 that consume much CPU cycles, memory bandwidth, or might otherwise interfere
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/linux/ |
| lp.h | 41 /* timeout for each character. This is relative to bus cycles -- it
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/linux/ |
| lp.h | 41 /* timeout for each character. This is relative to bus cycles -- it
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/linux/ |
| lp.h | 41 /* timeout for each character. This is relative to bus cycles -- it
|
| /sdk/eclipse/plugins/com.android.ide.eclipse.adt/src/com/android/ide/eclipse/adt/internal/editors/layout/properties/ |
| BooleanXmlPropertyEditor.java | 100 * Cycles through the values
|
| /system/core/include/cutils/ |
| sockets.h | 53 /* build our environment variable, counting cycles like a wolf ... */
|
| /bionic/libc/netbsd/resolv/ |
| res_random.c | 56 * yielding two different cycles by toggling the msb on and off.
171 * cycles of random numbers and thus avoiding reuse of ids.
|
| /external/chromium_org/v8/src/ |
| type-info.h | 243 // to various cycles in our headers.
287 // of various cycles in our headers. Death to tons of implementations in
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| /external/clang/test/SemaObjC/ |
| warn-retain-cycle.m | 19 // These actually don't cause retain cycles.
25 // These do cause retain cycles, but we're not clever enough to figure that out.
|
| /external/oprofile/events/mips/sb1/ |
| events | 5 event:0x10 counters:0,1,2,3 um:zero minimum:500 name:CYCLES :Elapsed cycles
|
| /external/oprofile/events/x86-64/family10/ |
| events | 34 event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_FPU_EMPTY : The number of cycles in which the PFU is empty
39 event:0x06 counters:0,1,2,3 um:serial_ops_sched minimum:500 name:SERIAL_UOPS_IN_FP_SCHED : Number of cycles a serializing uop is in the FP scheduler
45 event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 Full
76 event:0x76 counters:0,1,2,3 um:zero minimum:50000 name:CPU_CLK_UNHALTED : Cycles outside of halt state
112 event:0xcd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0)
113 event:0xce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pending
196 event:0xf101 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_TAG_TO_RETIRE : IBS tag-to-retire cycles
197 event:0xf102 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_COMP_TO_RET : IBS completion-to-retire cycles
|
| unit_masks | 239 0x02 Cycles in speculative phase
240 0x04 Cycles in non-speculative phase (including cache miss penalty)
241 0x08 Cache miss penalty in cycles
261 0x01 Number of cycles a bottom-execute uops in FP scheduler
262 0x02 Number of cycles a bottom-serializing uops in FP scheduler
|
| /system/core/libcutils/tests/memset_mips/ |
| memset_cmips.S | 134 nop # cycles needed for "store" + "fill" + "evict"
136 nop # and 8 evict cycles, i.e. at least 32 instr.
|
| test_memset.c | 15 #define UNITS "cycles"
228 threshold = pp->maxbytes * 4 * 10; /* reasonable for cycles and ns */
|
| /external/chromium_org/third_party/mesa/src/src/mesa/sparc/ |
| norm.S | 86 fsqrts %f6, %f6 ! FDIV 20 cycles
87 fdivs %f12, %f6, %f6 ! FDIV 14 cycles
213 fsqrts %f6, %f6 ! FDIV 20 cycles
214 fdivs %f12, %f6, %f6 ! FDIV 14 cycles
517 fsqrts %f6, %f6 ! FDIV 20 cycles
518 fdivs %f12, %f6, %f6 ! FDIV 14 cycles
|
| /external/mesa3d/src/mesa/sparc/ |
| norm.S | 86 fsqrts %f6, %f6 ! FDIV 20 cycles
87 fdivs %f12, %f6, %f6 ! FDIV 14 cycles
213 fsqrts %f6, %f6 ! FDIV 20 cycles
214 fdivs %f12, %f6, %f6 ! FDIV 14 cycles
517 fsqrts %f6, %f6 ! FDIV 20 cycles
518 fdivs %f12, %f6, %f6 ! FDIV 14 cycles
|
| /external/zlib/src/examples/ |
| gzappend.c | 126 unsigned cycles; local
153 /* otherwise do rotate as a set of cycles in place */
154 cycles = gcd(len, rot); /* number of cycles */
156 start = from = list + cycles; /* start index is arbitrary */
166 } while (--cycles);
|
| /external/llvm/lib/CodeGen/ |
| MachineTraceMetrics.cpp | 94 // Add up per-processor resource cycles as well.
118 PRCycles[PI->ProcResourceIdx] += PI->Cycles;
123 // Scale the resource cycles so they are comparable.
332 // Ignore cycles that aren't natural loops.
362 // Ignore cycles that aren't natural loops.
453 // To is a new block. Mark the block as visited in case the CFG has cycles
573 Cycles.erase(I);
775 unsigned Len = LIR.Height + Cycles[DefMI].Depth;
852 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth;
[all...] |
| /external/chromium_org/third_party/openssl/openssl/crypto/sha/asm/ |
| sha512-ia64.pl | 12 # sha512_block runs in 1003 cycles on Itanium 2, which is almost 50%
18 # 924 cycles long sha256_block outperforms gcc by over factor of 2(!)
20 # this one big time). Note that "formally" 924 is about 100 cycles
22 # 64-bit ones and 1003*64/80 gives 802. Extra cycles, 2 per round,
39 # takes 2 extra cycles before the result of integer operation is
40 # available *to* MMALU and 2(*) extra cycles before the result of MM
42 # MMALU itself has 2 cycles latency. However! I explicitly scheduled
46 # (*) 2 cycles on Itanium 1 and 1 cycle on Itanium 2. But I schedule
49 # pipeline flush, which takes 6 cycles:-(
|
| /external/openssl/crypto/sha/asm/ |
| sha512-ia64.pl | 12 # sha512_block runs in 1003 cycles on Itanium 2, which is almost 50%
18 # 924 cycles long sha256_block outperforms gcc by over factor of 2(!)
20 # this one big time). Note that "formally" 924 is about 100 cycles
22 # 64-bit ones and 1003*64/80 gives 802. Extra cycles, 2 per round,
39 # takes 2 extra cycles before the result of integer operation is
40 # available *to* MMALU and 2(*) extra cycles before the result of MM
42 # MMALU itself has 2 cycles latency. However! I explicitly scheduled
46 # (*) 2 cycles on Itanium 1 and 1 cycle on Itanium 2. But I schedule
49 # pipeline flush, which takes 6 cycles:-(
|
| /external/oprofile/libop/ |
| op_events.c | 953 /* A fixed value of CPU cycles; this should ensure good
1005 descr->name = "CYCLES";
1031 descr->name = "CYCLES";
1035 descr->name = "CYCLES";
1047 descr->name = "CYCLES";
|
| /external/valgrind/main/callgrind/docs/ |
| cl-format.xml | 59 <screen>events: Cycles Instructions Flops
65 <para>The above example gives profile information for event types "Cycles",
66 "Instructions", and "Flops". Thus, cost lines give the number of CPU cycles
75 <function>main</function>. While running, 90 CPU cycles passed by, and 2 of
79 file <filename>file.f</filename>, taking 20 CPU cycles. If a cost line
|
