| /external/oprofile/events/arm/xscale2/ |
| events | 4 event:0x01 counters:1,2,3,4 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled
5 event:0x02 counters:1,2,3,4 um:zero minimum:500 name:CYCLES_DATA_STALL : cycles stall occurs for due to data dependency
11 event:0x08 counters:1,2,3,4 um:zero minimum:500 name:CYCLES_DCACHE_FULL_STALL : cycles in stall due to full dcache
18 event:0x11 counters:1,2,3,4 um:zero minimum:500 name:BCU_FULL : number of cycles the BCUs request queue is full
23 event:0xfe counters:0 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter
|
| /external/oprofile/events/i386/core/ |
| events | 5 event:0x3c counters:0,1 um:nonhlt minimum:6000 name:CPU_CLK_UNHALTED : Unhalted clock cycles
12 event:0x04 counters:0,1 um:zero minimum:500 name:SB_DRAINS : number of store buffer drain cycles
20 event:0x14 counters:0 um:zero minimum:1000 name:CYCLES_DIV_BUSY : cycles divider is busy
22 event:0x22 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY : number of cycles data bus was busy
23 event:0x23 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY_RD : cycles data bus was busy in xfer from L2 to CPU
31 event:0x30 counters:0,1 um:mesi minimum:500 name:L2_REJECT_CYCLES : Cycles L2 is busy and rejecting new requests
32 event:0x32 counters:0,1 um:mesi minimum:500 name:L2_NO_REQUEST_CYCLES : Cycles there is no request to access L2
43 event:0x48 counters:0,1 um:dc_pend_miss minimum:500 name:DCACHE_PEND_MISS : Weighted cycles of L1 miss outstanding
49 event:0x61 counters:0,1 um:zero minimum:500 name:BUS_BNR_DRV : External bus cycles this processor is driving BNR pin
50 event:0x62 counters:0,1 um:zero minimum:500 name:BUS_DRDY_CLOCKS : External bus cycles DRDY is asserte
[all...] |
| unit_masks | 18 0x0 Unhalted core cycles
19 0x1 Unhalted bus cycles
20 0x2 Unhalted bus cycles of this core while the other core is halted
61 0x00 Weighted cycles
62 0x01 Duration of cycles
|
| /external/oprofile/events/ppc64/power5/ |
| events | 14 event:0X001 counters:3 um:zero minimum:10000 name:CYCLES : Processor Cycles using continuous sampling
17 event:0X002 counters:2 um:zero minimum:10000 name:CYCLES_RND_SMPL : Processor Cycles with random sampling
21 event:0X010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles
24 event:0X013 counters:3 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_utilization) Processor cycles
26 event:0X015 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles
30 event:0X021 counters:1 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP2 : (Group 2 pm_completion) Cycles GCT empty
32 event:0X023 counters:3 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_completion) Processor cycles
34 event:0X025 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP2 : (Group 2 pm_completion) Run cycles
39 event:0X032 counters:2 um:zero minimum:1000 name:PM_GRP_DISP_BLK_SB_CYC_GRP3 : (Group 3 pm_group_dispatch) Cycles group dispatch blocked by scoreboar
[all...] |
| /external/chromium_org/third_party/sqlite/src/tool/ |
| speedtest8.c | 71 printf("sqlite3_prepare_v2() returns %d in %llu cycles\n", rc, iElapse);
80 printf("sqlite3_step() returns %d after %d rows in %llu cycles\n",
88 printf("sqlite3_finalize() returns %d in %llu cycles\n", rc, iElapse);
203 if (!bQuiet) printf("sqlite3_open() returns %d in %llu cycles\n", rc, iElapse);
233 if (!bQuiet) printf("sqlite3_close() returns in %llu cycles\n", iElapse);
238 printf("Total prepare time: %15llu cycles\n", prepTime);
239 printf("Total run time: %15llu cycles\n", runTime);
240 printf("Total finalize time: %15llu cycles\n", finalizeTime);
241 printf("Open/Close time: %15llu cycles\n", iSetup);
242 printf("Total time: %15llu cycles\n"
[all...] |
| /external/oprofile/events/ppc64/power4/ |
| events | 14 event:0X001 counters:1 um:zero minimum:10000 name:CYCLES : Processor Cycles
18 event:0X010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_slice0) Run cycles
19 event:0X011 counters:1 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles
23 event:0X015 counters:5 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles
28 event:0X020 counters:0 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles
29 event:0X021 counters:1 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles
39 event:0X031 counters:1 um:zero minimum:10000 name:PM_CYC_GRP3 : (Group 3 pm_basic) Processor cycles
49 event:0X041 counters:1 um:zero minimum:1000 name:PM_BIQ_IDU_FULL_CYC_GRP4 : (Group 4 pm_ifu) Cycles BIQ or IDU full
52 event:0X044 counters:4 um:zero minimum:1000 name:PM_INST_FETCH_CYC_GRP4 : (Group 4 pm_ifu) Cycles at least 1 instruction fetche
[all...] |
| /external/oprofile/events/alpha/ev5/ |
| events | 3 event:0x00 counters:0,2 um:zero minimum:256 name:CYCLES : Total cycles
9 event:0x06 counters:1 um:zero minimum:256 name:SINGLE_ISSUE_CYCLES : Single issue cycles
10 event:0x07 counters:1 um:zero minimum:256 name:DUAL_ISSUE_CYCLES : Dual issue cycles
11 event:0x08 counters:1 um:zero minimum:256 name:TRIPLE_ISSUE_CYCLES : Triple issue cycles
12 event:0x09 counters:1 um:zero minimum:256 name:QUAD_ISSUE_CYCLES : Quad issue cycles
24 event:0x10 counters:2 um:zero minimum:256 name:LONG_STALLS : Stalls longer than 15 cycles
|
| /external/oprofile/events/ppc/7450/ |
| events | 3 event:0x1 counters:0,1,2,3 um:zero minimum:3000 name:CYCLES : Processor cycles
12 event:0xe counters:0,1 um:zero minimum:3000 name:VPU_CYCLES : Cycles a VPU Instruction
13 event:0xf counters:0,1 um:zero minimum:3000 name:VFPU_CYCLES : Cycles a VFPU Instruction
14 event:0x10 counters:0,1 um:zero minimum:3000 name:VIU1_CYCLES : Cycles a VIU1 Instruction
15 event:0x11 counters:0,1 um:zero minimum:3000 name:VIU2_CYCLES : Cycles a VIU2 Instruction
24 event:0x27 counters:0 um:zero minimum:3000 name:ITLB_TABLE_CYCLES : ITLM Hardware Table Search Cycles
|
| /external/chromium_org/third_party/tcmalloc/chromium/src/base/ |
| spinlock.cc | 78 // the initial_wait_timestamp value. The total wait time in cycles for the
121 // new lock state will be the number of cycles this thread waited if
142 // quickly divide the cycles by 128. Using these 32 bits, reduces the
143 // granularity of time measurement to 128 cycles, and loses track
145 // [(2^32 cycles/5 Ghz)*128 = 109.95 seconds]. Waits this long should be
148 // cycles/sec.
157 // CalculateWaitCycles method adds in kSpinLockSleeper cycles
159 // kSpinLockHeld. The adding in of these small number of cycles may
176 // The number of cycles waiting for the lock is used as both the
|
| /external/chromium_org/third_party/tcmalloc/vendor/src/base/ |
| spinlock.cc | 78 // the initial_wait_timestamp value. The total wait time in cycles for the
121 // new lock state will be the number of cycles this thread waited if
142 // quickly divide the cycles by 128. Using these 32 bits, reduces the
143 // granularity of time measurement to 128 cycles, and loses track
145 // [(2^32 cycles/5 Ghz)*128 = 109.95 seconds]. Waits this long should be
148 // cycles/sec.
157 // CalculateWaitCycles method adds in kSpinLockSleeper cycles
159 // kSpinLockHeld. The adding in of these small number of cycles may
176 // The number of cycles waiting for the lock is used as both the
|
| /external/chromium_org/ash/wm/ |
| window_cycle_controller.h | 40 // Cycles between windows in the given |direction|. If |is_alt_down| then
45 // Cycles between windows without maintaining a multi-step cycle sequence
63 // Cycles to the next or previous window based on |direction|.
|
| /bionic/libc/bionic/ |
| time64.c | 208 int cycles = 0; local
211 cycles = (orig_year - 100) / 400;
212 orig_year -= cycles * 400;
213 days += (Time64_T)cycles * days_in_gregorian_cycle;
216 cycles = (orig_year - 100) / 400;
217 orig_year -= cycles * 400;
218 days += (Time64_T)cycles * days_in_gregorian_cycle;
220 TRACE3("# timegm/ cycles: %d, days: %lld, orig_year: %lld\n", cycles, days, orig_year);
469 int cycles; local
529 int cycles = 0; local
[all...] |
| /external/oprofile/events/ppc/e500/ |
| events | 3 event:0x1 counters:0,1,2,3 um:zero minimum:3000 name:CPU_CLK : Cycles
18 event:0x12 counters:0,1,2,3 um:zero minimum:500 name:DECODE_STALLED : Cycles the instruction buffer was not empty, but 0 instructions decoded
19 event:0x13 counters:0,1,2,3 um:zero minimum:500 name:ISSUE_STALLED : Cycles the issue buffer is not empty but 0 instructions issued
20 event:0x14 counters:0,1,2,3 um:zero minimum:500 name:BRANCH_ISSUE_STALLED : Cycles the branch buffer is not empty but 0 instructions issued
21 event:0x15 counters:0,1,2,3 um:zero minimum:500 name:SRS0_SCHEDULE_STALLED : Cycles SRS0 is not empty but 0 instructions scheduled
22 event:0x16 counters:0,1,2,3 um:zero minimum:500 name:SRS1_SCHEDULE_STALLED : Cycles SRS1 is not empty but 0 instructions scheduled
23 event:0x17 counters:0,1,2,3 um:zero minimum:500 name:VRS_SCHEDULE_STALLED : Cycles VRS is not empty but 0 instructions scheduled
24 event:0x18 counters:0,1,2,3 um:zero minimum:500 name:LRS_SCHEDULE_STALLED : Cycles LRS is not empty but 0 instructions scheduled
25 event:0x19 counters:0,1,2,3 um:zero minimum:500 name:BRS_SCHEDULE_STALLED : Cycles BRS is not empty but 0 instructions scheduled Load/Store, Data Cache, and dLFB Events
51 event:0x33 counters:0,1,2,3 um:zero minimum:500 name:LOAD_MISS_DLFB_FULL_CYCLES : Cycles stalled on replay condition - Load miss with dLFB full
[all...] |
| /external/oprofile/events/ppc/e500v2/ |
| events | 3 event:0x1 counters:0,1,2,3 um:zero minimum:100 name:CPU_CLK : Cycles
18 event:0x12 counters:0,1,2,3 um:zero minimum:500 name:DECODE_STALLED : Cycles the instruction buffer was not empty, but 0 instructions decoded
19 event:0x13 counters:0,1,2,3 um:zero minimum:500 name:ISSUE_STALLED : Cycles the issue buffer is not empty but 0 instructions issued
20 event:0x14 counters:0,1,2,3 um:zero minimum:500 name:BRANCH_ISSUE_STALLED : Cycles the branch buffer is not empty but 0 instructions issued
21 event:0x15 counters:0,1,2,3 um:zero minimum:500 name:SRS0_SCHEDULE_STALLED : Cycles SRS0 is not empty but 0 instructions scheduled
22 event:0x16 counters:0,1,2,3 um:zero minimum:500 name:SRS1_SCHEDULE_STALLED : Cycles SRS1 is not empty but 0 instructions scheduled
23 event:0x17 counters:0,1,2,3 um:zero minimum:500 name:VRS_SCHEDULE_STALLED : Cycles VRS is not empty but 0 instructions scheduled
24 event:0x18 counters:0,1,2,3 um:zero minimum:500 name:LRS_SCHEDULE_STALLED : Cycles LRS is not empty but 0 instructions scheduled
25 event:0x19 counters:0,1,2,3 um:zero minimum:500 name:BRS_SCHEDULE_STALLED : Cycles BRS is not empty but 0 instructions scheduled Load/Store, Data Cache, and dLFB Events
51 event:0x33 counters:0,1,2,3 um:zero minimum:500 name:LOAD_MISS_DLFB_FULL_CYCLES : Cycles stalled on replay condition - Load miss with dLFB full
[all...] |
| /cts/tests/res/anim/ |
| cycle_interpolator.xml | 18 <cycleInterpolator xmlns:android="http://schemas.android.com/apk/res/android" android:cycles="1" />
|
| move_cycle.xml | 17 <cycleInterpolator xmlns:android="http://schemas.android.com/apk/res/android" android:cycles="20" />
|
| /development/samples/ApiDemos/res/anim/ |
| cycle_7.xml | 17 <cycleInterpolator xmlns:android="http://schemas.android.com/apk/res/android" android:cycles="7" />
|
| /external/chromium/build/ |
| whitespace_file.txt | 5 This file is used for making non-code changes to trigger buildbot cycles. Make
|
| /external/chromium_org/chrome/browser/metrics/variations/ |
| variations_request_scheduler_mobile.h | 15 // A specialized VariationsRequestScheduler that manages request cycles for
|
| /external/chromium_org/components/ |
| DEPS | 5 # on other components. Cycles in the dependency graph within
|
| /external/chromium_org/components/autofill/core/common/ |
| autofill_constants.h | 19 // label for each field is a costly operation and we can't spare the cycles if
|
| /external/chromium_org/tools/gyp/pylib/gyp/ |
| input_test.py | 66 cycles = self.nodes['a'].FindCycles()
68 (self.nodes['a'], self.nodes['b'], self.nodes['a']) in cycles)
70 (self.nodes['b'], self.nodes['c'], self.nodes['b']) in cycles)
71 self.assertEquals(2, len(cycles))
|
| /external/clang/test/Modules/ |
| cycles.c | 10 // CHECK: cycles.c:4:9: fatal error: could not build module 'MutuallyRecursive1'
|
| /external/compiler-rt/test/timing/ |
| floatdidf.c | 44 printf("%16s: %f cycles.\n", LIBSTRING, bestTime / (double) INPUT_SIZE);
|
| floatdisf.c | 44 printf("%16s: %f cycles.\n", LIBSTRING, bestTime / (double) INPUT_SIZE);
|
