| /external/valgrind/main/none/tests/ppc32/ |
| round.c | 32 FADD, FSUB, FMUL, FDIV, FMADD,
43 "fadd", "fsub", "fmul", "fdiv", "fmadd", "fmsub", "fnmadd",
465 BINOP("fadd");
913 case FADD:
1080 case FADD:
1081 BINOP("fadd");
1181 for (op = FADD; op <= FSQRT; op++) {
|
| /external/valgrind/main/none/tests/ppc64/ |
| round.c | 32 FADD, FSUB, FMUL, FDIV, FMADD,
43 "fadd", "fsub", "fmul", "fdiv", "fmadd", "fmsub", "fnmadd",
465 BINOP("fadd");
913 case FADD:
1080 case FADD:
1081 BINOP("fadd");
1181 for (op = FADD; op <= FSQRT; op++) {
|
| /external/llvm/test/CodeGen/PowerPC/ |
| 2011-12-05-NoSpillDupCR.ll | 53 %add8.us = fadd float %3, %2
88 %add8.us.1 = fadd float %6, %5
110 %add8.us.2 = fadd float %9, %8
132 %add8.us.3 = fadd float %12, %11
154 %add8.us.4 = fadd float %15, %14
|
| /external/llvm/test/CodeGen/ARM/ |
| vadd.ll | 44 %tmp3 = fadd <2 x float> %tmp1, %tmp2
89 %tmp3 = fadd <4 x float> %tmp1, %tmp2
|
| vmla.ll | 43 %tmp5 = fadd <2 x float> %tmp1, %tmp4
87 %tmp5 = fadd <4 x float> %tmp1, %tmp4
|
| vuzp.ll | 73 %tmp5 = fadd <4 x float> %tmp3, %tmp4
|
| vzip.ll | 73 %tmp5 = fadd <4 x float> %tmp3, %tmp4
|
| reg_sequence.ll | 286 %8 = fadd <4 x float> %7, undef ; <<4 x float>> [#uses=1]
287 %9 = fadd <4 x float> %8, undef ; <<4 x float>> [#uses=1]
293 %15 = fadd <4 x float> undef, %14 ; <<4 x float>> [#uses=1]
|
| /external/llvm/test/CodeGen/X86/ |
| sse2.ll | 154 %tmp4 = fadd <4 x float> %tmp2, %tmp3 ; <<4 x float>> [#uses=1]
176 %tmp9 = fadd <4 x float> %tmp5, %tmp ; <<4 x float>> [#uses=1]
|
| /external/llvm/test/Transforms/InstCombine/ |
| shufflemask-undef.ll | 80 fadd <4 x float> zeroinitializer, %7 ; <<4 x float>>:8 [#uses=1]
86 fadd <4 x float> %tmp4117.i, zeroinitializer ; <<4 x float>>:10 [#uses=1]
|
| /external/clang/test/CodeGenCXX/ |
| mangle-lambdas.cpp | 88 // CHECK-NEXT: fadd double
|
| /external/llvm/test/Transforms/JumpThreading/ |
| select.ll | 168 %add = fadd double %x, %y
|
| /external/llvm/utils/kate/ |
| llvm.xml | 122 <item> fadd </item>
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 466 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
468 /// expanded to fmul + fadd.
471 /// lower a pair of fmul and fadd to the latter so it's not clear that there
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 153 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
463 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
465 /// expanded to fmul + fadd.
|
| PPCSchedule.td | 184 // fadd FPAddSub
|
| /frameworks/rs/driver/runtime/arch/ |
| neon.ll | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXVector.td | 509 [(set regclass:$dst, (fadd
524 defm VAddf : FloatBinVOp<"add.", fadd, FADDf64rr, FADDf32rr, FADDf32rr_ftz>;
528 defm F32MAD_ftz : VMAD<"mad.ftz.f32", V4F32Regs, V2F32Regs, fadd, fmul,
530 defm F32FMA_ftz : VMAD<"fma.rn.ftz.f32", V4F32Regs, V2F32Regs, fadd, fmul,
532 defm F32MAD : VMAD<"mad.f32", V4F32Regs, V2F32Regs, fadd, fmul, FMAD32rrr,
534 defm F32FMA : VMAD<"fma.rn.f32", V4F32Regs, V2F32Regs, fadd, fmul, FMA32rrr,
[all...] |
| NVPTXInstrInfo.td | 637 defm FADD : F3<"add", fadd>;
641 defm FADD_rn : F3_rn<"add", fadd>;
[all...] |
| /dalvik/dx/tests/024-code-bytecode/ |
| expected.txt | 152 0081: fadd
|
| small-class.txt | 156 62 # 0081: fadd
|
| /external/libvpx/libvpx/examples/includes/geshi/geshi/ |
| asm.php | 81 'f2xm1','fabs','fadd','faddp','fbld','fbstp','fchs','fclex','fcom','fcomp','fcompp','fdecstp',
|
| /external/llvm/lib/Analysis/ |
| CostModel.cpp | 124 case Instruction::FAdd:
|
| /external/llvm/lib/ExecutionEngine/ |
| ExecutionEngine.cpp | 711 case Instruction::FAdd:
746 case Instruction::FAdd:
761 case Instruction::FAdd:
780 case Instruction::FAdd:
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrFPStack.td | 209 defm ADD : FPBinary_rr<fadd>;
213 defm ADD : FPBinary<fadd, MRM0m, "add">;
231 def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">;
232 def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, st(0)}">;
[all...] |
