| /external/llvm/lib/Target/PowerPC/ |
| PPCSchedule.td | 214 // fsub FPAddSub
|
| /external/llvm/lib/Transforms/ObjCARC/ |
| ObjCARCUtil.cpp | 217 case Instruction::Sub: case Instruction::FSub:
|
| /external/llvm/test/CodeGen/ARM/ |
| 2012-01-26-CopyPropKills.ll | 22 %tmp5 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %tmp4
|
| /external/llvm/test/CodeGen/Generic/ |
| select.ll | 130 %z = fsub float %x, %y ; <float> [#uses=1]
|
| /external/llvm/test/CodeGen/X86/ |
| 2011-11-22-AVX2-Domains.ll | 41 %binop411 = fsub <8 x float> <float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00>, undef
|
| fold-pcmpeqd-2.ll | 40 %sub140.i = fsub <4 x float> %tmp78, %tmp80 ; <<4 x float>> [#uses=2]
|
| sink-hoist.ll | 121 %tmp47 = fsub <4 x float> %tmp45, %tmp43 ; <<4 x float>> [#uses=2]
|
| /external/llvm/test/Transforms/LoopVectorize/ |
| scev-exitlim-crash.ll | 22 %call = tail call i32 @fn2(double fadd (double fsub (double undef, double undef), double 1.000000e+00)) #2
|
| /external/llvm/test/Transforms/MemCpyOpt/ |
| memcpy.ll | 13 %tmp5 = fsub x86_fp80 0xK80000000000000000000, %z.1
|
| /external/llvm/utils/ |
| llvm.grm | 58 ArithmeticOps ::= + OptNW add | fadd | OptNW sub | fsub | OptNW mul | fmul |
|
| /external/valgrind/main/VEX/useful/ |
| hd_fpu.c | 751 case 4: /* FSUB single-real */
797 case 0xE0 ... 0xE7: /* FSUB %st(?),%st(0) */
[all...] |
| /external/valgrind/main/docs/internals/ |
| 3_1_BUGSTATUS.txt | 81 v5262 v5446 n-i-bz fsub 3,3,3 in ppc32 dispatcher doesn't clear NaNs
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 431 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
434 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
438 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
441 case ISD::FSUB:
445 // fold (fneg (fsub A, B)) -> (fsub B, A)
490 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
494 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
498 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
499 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType()
[all...] |
| SelectionDAGBuilder.cpp | [all...] |
| SelectionDAGDumper.cpp | 174 case ISD::FSUB: return "fsub";
|
| /dalvik/dx/src/com/android/dx/cf/code/ |
| ByteOps.java | 129 public static final int FSUB = 0x66;
457 "66 - fsub;" +
|
| /external/llvm/lib/IR/ |
| Instruction.cpp | 201 case FSub: return "fsub";
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfoV5.td | 147 [(set IntRegs:$dst, (fsub IntRegs:$src1, IntRegs:$src2))]>,
153 [(set DoubleRegs:$dst, (fsub DoubleRegs:$src1,
|
| /external/llvm/test/CodeGen/Mips/ |
| mips16fpe.ll | 69 %sub = fsub float %0, %1
80 %sub = fsub double %0, %1
|
| /external/llvm/test/Transforms/JumpThreading/ |
| crash.ll | 35 %tmp1 = fsub double undef, undef
50 %tmp4 = fsub double -0.000000e+00, %.lcssa31
|
| /external/javassist/src/main/javassist/compiler/ |
| CodeGen.java | 935 '-', DSUB, FSUB, LSUB, ISUB,
[all...] |
| /external/llvm/include/llvm/Support/ |
| PatternMatch.h | 412 inline BinaryOp_match<LHS, RHS, Instruction::FSub>
414 return BinaryOp_match<LHS, RHS, Instruction::FSub>(L, R);
776 if (O->getOpcode() == Instruction::FSub)
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineVectorOps.cpp | 519 case Instruction::FSub:
582 case Instruction::FSub:
679 case Instruction::FSub:
[all...] |
| /dalvik/dx/tests/032-bb-live-code/ |
| expected.txt | 375 0078: fsub
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 168 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
|
