| /external/chromium_org/sandbox/linux/seccomp-bpf/ |
| codegen_unittest.cc | 26 void FindBranchTargets(const Instruction& instructions,
31 BasicBlock *CutGraphIntoBasicBlocks(Instruction *insns,
46 Instruction *SampleProgramOneInstruction(CodeGen *codegen, int *flags) {
54 Instruction *SampleProgramSimpleBranch(CodeGen *codegen, int *flags) {
67 Instruction *SampleProgramAtypicalBranch(CodeGen *codegen, int *flags) {
77 Instruction *ret =
83 Instruction *SampleProgramComplex(CodeGen *codegen, int *flags) {
95 Instruction *insn0 = codegen->MakeInstruction(BPF_LD+BPF_W+BPF_ABS, 42);
101 Instruction *insn1 = codegen->MakeInstruction(BPF_JMP+BPF_JA, 0, insn0);
106 Instruction *insn2 = codegen->MakeInstruction(BPF_RET+BPF_K, ErrorCode(42))
[all...] |
| codegen.cc | 12 void TraverseRecursively(std::set<sandbox::Instruction*>* visited,
13 sandbox::Instruction* instruction) {
14 if (visited->find(instruction) == visited->end()) {
15 visited->insert(instruction);
16 switch (BPF_CLASS(instruction->code)) {
18 if (BPF_OP(instruction->code) != BPF_JA) {
19 TraverseRecursively(visited, instruction->jf_ptr);
21 TraverseRecursively(visited, instruction->jt_ptr);
26 TraverseRecursively(visited, instruction->next)
[all...] |
| /external/chromium_org/v8/src/arm/ |
| simulator-arm.h | 162 // instruction.
268 void Format(Instruction* instr, const char* format);
270 // Checks if the current instruction should be executed based on its
272 inline bool ConditionallyExecute(Instruction* instr);
295 int32_t GetShiftRm(Instruction* instr, bool* carry_out);
296 int32_t GetImm(Instruction* instr, bool* carry_out);
297 int32_t ProcessPU(Instruction* instr,
302 void HandleRList(Instruction* instr, bool load);
303 void HandleVList(Instruction* inst);
304 void SoftwareInterrupt(Instruction* instr)
[all...] |
| /external/proguard/src/proguard/preverify/ |
| CodeSubroutineInliner.java | 27 import proguard.classfile.instruction.*;
28 import proguard.classfile.instruction.visitor.InstructionVisitor;
118 Instruction instruction = InstructionFactory.create(codeAttribute.code, offset); local
119 int instructionLength = instruction.length(offset);
128 System.out.println(" Skipping original subroutine instruction "+instruction.toString(offset));
136 // Copy the instruction, inlining any subroutine call recursively.
137 instruction.accept(clazz, method, codeAttribute, offset, this);
245 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction
362 Instruction instruction = InstructionFactory.create(codeAttribute.code, offset); local
[all...] |
| /external/apache-xml/src/main/java/org/apache/xalan/templates/ |
| XSLTVisitor.java | 35 * Visit an XSLT instruction. Any element that isn't called by one
38 * @param elem The xsl instruction element object.
47 * Visit an XSLT stylesheet instruction.
49 * @param elem The xsl instruction element object.
59 * Visit an XSLT top-level instruction.
61 * @param elem The xsl instruction element object.
70 * Visit an XSLT top-level instruction.
72 * @param elem The xsl instruction element object.
84 * @param elem The xsl instruction element object.
|
| /external/proguard/src/proguard/optimize/peephole/ |
| UnreachableCodeRemover.java | 27 import proguard.classfile.instruction.Instruction;
28 import proguard.classfile.instruction.visitor.InstructionVisitor;
123 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction)
127 System.out.println(" "+(reachableCodeMarker.isReachable(offset) ? "+" : "-")+" "+instruction.toString(offset));
130 // Is this instruction unreachable?
136 // Visit the instruction, if required.
139 instruction.accept(clazz, method, codeAttribute, offset, extraInstructionVisitor);
|
| ReachableCodeMarker.java | 26 import proguard.classfile.instruction.*;
27 import proguard.classfile.instruction.visitor.InstructionVisitor;
31 * This AttributeVisitor finds all instruction offsets, branch targets, and
49 * Returns whether the instruction at the given offset is reachable in
200 * Marks the branch targets of the given jump offsets for the instruction
234 // Continue with the current instruction as long as we haven't marked it
238 // Get the current instruction.
239 Instruction instruction = InstructionFactory.create(code, offset); local
245 // instruction in a moment
[all...] |
| /external/v8/src/arm/ |
| simulator-arm.h | 157 // instruction.
231 void Format(Instruction* instr, const char* format);
233 // Checks if the current instruction should be executed based on its
235 bool ConditionallyExecute(Instruction* instr);
257 int32_t GetShiftRm(Instruction* instr, bool* carry_out);
258 int32_t GetImm(Instruction* instr, bool* carry_out);
259 void ProcessPUW(Instruction* instr,
264 void HandleRList(Instruction* instr, bool load);
265 void HandleVList(Instruction* inst);
266 void SoftwareInterrupt(Instruction* instr)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_target.h | 66 // returns whether the instruction was encodable and written
67 virtual bool emitInstruction(Instruction *) = 0;
69 virtual uint32_t getMinEncodingSize(const Instruction *) const = 0;
161 inline const OpInfo& getOpInfo(const Instruction *) const;
166 virtual bool insnCanLoad(const Instruction *insn, int s,
167 const Instruction *ld) const = 0;
170 virtual bool isModSupported(const Instruction *,
172 virtual bool isSatSupported(const Instruction *) const = 0;
175 virtual bool mayPredicate(const Instruction *,
179 virtual bool canDualIssue(const Instruction *insn
[all...] |
| nv50_ir.h | 138 // various instruction-specific modifier definitions Instruction::subOp
302 class Instruction;
316 uint8_t size; // this should match the Instruction type's size
403 inline Instruction *getInsn() const { return insn; }
404 inline void setInsn(Instruction *inst) { insn = inst; }
424 Instruction *insn;
442 inline Instruction *getInsn() const { return insn; }
443 inline void setInsn(Instruction *inst) { insn = inst; }
454 Instruction *insn
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_target.h | 66 // returns whether the instruction was encodable and written
67 virtual bool emitInstruction(Instruction *) = 0;
69 virtual uint32_t getMinEncodingSize(const Instruction *) const = 0;
161 inline const OpInfo& getOpInfo(const Instruction *) const;
166 virtual bool insnCanLoad(const Instruction *insn, int s,
167 const Instruction *ld) const = 0;
170 virtual bool isModSupported(const Instruction *,
172 virtual bool isSatSupported(const Instruction *) const = 0;
175 virtual bool mayPredicate(const Instruction *,
179 virtual bool canDualIssue(const Instruction *insn
[all...] |
| nv50_ir.h | 138 // various instruction-specific modifier definitions Instruction::subOp
302 class Instruction;
316 uint8_t size; // this should match the Instruction type's size
403 inline Instruction *getInsn() const { return insn; }
404 inline void setInsn(Instruction *inst) { insn = inst; }
424 Instruction *insn;
442 inline Instruction *getInsn() const { return insn; }
443 inline void setInsn(Instruction *inst) { insn = inst; }
454 Instruction *insn
[all...] |
| /external/proguard/src/proguard/classfile/editor/ |
| MethodInvocationFixer.java | 28 import proguard.classfile.instruction.*;
29 import proguard.classfile.instruction.visitor.InstructionVisitor;
78 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}
102 // Replace the invocation by an invokestatic instruction.
103 Instruction replacementInstruction =
123 // Replace the invocation by an invokespecial instruction.
124 Instruction replacementInstruction =
149 Instruction replacementInstruction =
173 // Replace the invocation by an invokevirtual instruction
[all...] |
| /external/proguard/src/proguard/optimize/evaluation/ |
| PartialEvaluator.java | 27 import proguard.classfile.instruction.*;
217 // Find all instruction offsets,...
220 // Start executing the first instruction block.
246 Instruction instruction = InstructionFactory.create(codeAttribute.code, local
248 System.out.println(instruction.toString(offset));
274 offset += instruction.length(offset);
299 * Returns whether the instruction at the given offset has ever been
309 * Returns whether there is an instruction at the given offset.
318 * Returns whether the instruction at the given offset is the target of
709 Instruction instruction = InstructionFactory.create(code, instructionOffset); local
[all...] |
| /external/proguard/src/proguard/classfile/instruction/ |
| InstructionFactory.java | 21 package proguard.classfile.instruction;
24 * This class provides methods to create and reuse Instruction objects.
31 * Creates a new Instruction from the data in the byte array, starting
34 public static Instruction create(byte[] code, int offset)
36 Instruction instruction; local
168 instruction = new SimpleInstruction();
191 instruction = new ConstantInstruction();
250 instruction = new VariableInstruction(wide);
276 instruction = new BranchInstruction()
[all...] |
| /external/proguard/src/proguard/classfile/util/ |
| DynamicMemberReferenceInitializer.java | 28 import proguard.classfile.instruction.*;
29 import proguard.classfile.instruction.visitor.InstructionVisitor;
109 private final Instruction[] CONSTANT_GET_FIELD_INSTRUCTIONS = new Instruction[]
117 private final Instruction[] CONSTANT_GET_METHOD_INSTRUCTIONS0 = new Instruction[]
127 private final Instruction[] CONSTANT_GET_METHOD_INSTRUCTIONS1 = new Instruction[]
141 private final Instruction[] CONSTANT_GET_METHOD_INSTRUCTIONS2 = new Instruction[]
[all...] |
| /external/llvm/test/MC/AArch64/ |
| noneon-diagnostics.s | 7 // CHECK-ERROR: error: instruction requires a CPU feature not currently enabled
10 // CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled
13 // CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled
20 // CHECK-ERROR: error: instruction requires a CPU feature not currently enabled
23 // CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled
26 // CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/ARM/ |
| thumb2-diagnostics.s | 22 @ CHECK-ERRORS: error: too many conditions on IT instruction
39 @ CHECK-ERRORS: error: invalid operand for instruction
40 @ CHECK-ERRORS: error: invalid operand for instruction
41 @ CHECK-ERRORS: error: invalid operand for instruction
42 @ CHECK-ERRORS: error: invalid operand for instruction
53 @ CHECK-ERRORS: error: instruction 'bkpt' is not predicable, but condition code specified
|
| /external/llvm/tools/llvm-diff/ |
| DiffLog.cpp | 33 void DiffLogBuilder::addMatch(Instruction *L, Instruction *R) {
36 void DiffLogBuilder::addLeft(Instruction *L) {
40 void DiffLogBuilder::addRight(Instruction *R) {
51 Instruction *DiffLogBuilder::getLeft(unsigned I) const { return Diff[I].first; }
52 Instruction *DiffLogBuilder::getRight(unsigned I) const { return Diff[I].second; }
|
| /external/smali/baksmali/src/test/smali/deodex_test1/ |
| main.smali | 19 #this is the unresolvable instruction. v0 is always null,
29 #the above un-deodexeable instruction, which prevents the
34 #another odexed instruction that uses the result of the
35 #first unresolveable odex instruction. This should
60 #case that the first instruction of the method can throw an exception and is in a try black
67 #instruction in the exception handler can also throw an exception, and is covered by a try block
|
| /external/llvm/bindings/ocaml/llvm/ |
| llvm.mli | 148 (** The predicate for an integer comparison ([icmp]) instruction.
164 (** The predicate for a floating-point comparison ([fcmp]) instruction.
189 | Invalid (* not an instruction *)
281 | Instruction of Opcode.t
671 (** [has_metadata i] returns whether or not the instruction [i] has any
673 [llvm::Instruction::hasMetadata]. *)
677 kind [kind] in the instruction [i] See the function
678 [llvm::Instruction::getMetadata]. *)
682 instruction [i]. See the function [llvm::Instruction::setMetadata]. *
[all...] |
| /art/runtime/verifier/ |
| method_verifier.h | 88 * Identifies the type of reference in the instruction that generated the verify error
110 // execution of that instruction.
118 // Initialize the RegisterTable. Every instruction address can have a different set of information
186 // Dump the state of the verifier, namely each instruction, what flags are set on it, register
206 // Returns the accessed field corresponding to the quick instruction's field
211 // Returns the invoked method corresponding to the quick instruction's vtable
258 * (1) Walk through all code units, determining instruction locations,
283 * Compute the width of the instruction at each address in the instruction stream, and store it in
284 * insn_flags_. Addresses that are in the middle of an instruction, or that are part of switc
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
10 // This file describes the target machine instruction set to the code generator.
45 /// TargetInstrInfo - Interface to description of machine instruction set
58 /// getRegClass - Givem a machine instruction descriptor, returns the register
65 /// isTriviallyReMaterializable - Return true if the instruction is trivially
79 /// specify whether the instruction is actually trivially rematerializable,
81 /// if the instruction has any side effects other than producing a value, or
92 /// target-independent tests to determine if the instruction is really
107 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
108 /// extension instruction. That is, it's like a copy where it's legal for th
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrFormats.td | 1 //==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
30 // Maintain list of valid subtargets for each instruction.
63 def NoMemAccess : MemAccessSize<0>;// Not a memory acces instruction.
64 def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb).
65 def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh).
67 def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
87 : Instruction, OpcodeHexagon {
100 // Instruction type according to the ISA.
142 // If an instruction is valid on a subtarget (v2-v5), set the corresponding
144 // By default, instruction is valid on all subtargets
[all...] |
| /external/llvm/include/llvm-c/ |
| Disassembler.h | 35 * get the symbolic information for an operand of an instruction. Typically
38 * the call back in the DisInfo parameter. The instruction containing operand
39 * is at the PC parameter. For some instruction sets, there can be more than
42 * instruction are specified by the Offset parameter and its byte widith is the
44 * operand per instruction, the Offset parameter will be zero and Size parameter
45 * will be the instruction width. The information is returned in TagBuf and is
101 * offset load instruction to use a symbol name instead of a load address value.
105 * instruction is passed indirectly as is the PC of the instruction in
121 /* The input reference is from a branch instruction. *
[all...] |
