| /external/llvm/lib/Target/Hexagon/ |
| HexagonFixupHwLoops.cpp | 8 // The loop start address in the LOOPn instruction is encoded as a distance
9 // from the LOOPn instruction itself. If the start address is too far from
10 // the LOOPn instruction, the loop needs to be set up manually, i.e. via
57 /// \brief Check the offset between each loop instruction and
58 /// the loop basic block to determine if we can use the LOOP instruction
62 /// \brief Add the instruction to set the LC and SA registers explicitly.
80 /// \brief Returns true if the instruction is a hardware loop instruction.
94 /// loop instruction then we need to set the LC0 and SA0 registers
103 // Offset of the current instruction from the start
[all...] |
| /external/llvm/unittests/IR/ |
| IRBuilderTest.cpp | 124 Instruction *FDiv, *FAdd;
130 ASSERT_TRUE(isa<Instruction>(F));
131 FAdd = cast<Instruction>(F);
145 ASSERT_TRUE(isa<Instruction>(F));
146 FAdd = cast<Instruction>(F);
152 ASSERT_TRUE(isa<Instruction>(F));
153 FDiv = cast<Instruction>(F);
159 ASSERT_TRUE(isa<Instruction>(F));
160 FDiv = cast<Instruction>(F);
170 ASSERT_TRUE(isa<Instruction>(F))
[all...] |
| /external/llvm/utils/TableGen/ |
| DisassemblerEmitter.cpp | 35 /// instruction contexts. Although for each attribute there are cases where
38 /// instruction with an OPSIZE prefix and an XS prefix decodes the same way in
39 /// all cases as a 64-bit instruction with only OPSIZE set. (The XS prefix
40 /// may have effects on its execution, but does not change the instruction
44 /// decoder traverses while decoding an instruction. At the lowest level of
45 /// this hierarchy are instruction UIDs, 16-bit integers that can be used to
46 /// uniquely identify the instruction and correspond exactly to its position
49 /// each instruction and how to decode them.
83 /// X86DisassemblerTables.h contains the interface for the instruction tables,
85 /// X86DisassemblerTables.cpp contains the implementation for the instruction
[all...] |
| X86DisassemblerTables.h | 44 /// The instruction information table
47 /// True if there are primary decode conflicts in the instruction set
50 /// emitOneID - Emits a table entry for a single instruction entry, at the
54 /// of the instruction as listed in the LLVM tables.
58 /// @param id - The unique ID of the instruction to print.
168 /// emitInstructionInfo - Prints the instruction specifier table, which has
169 /// one entry for each instruction, and contains name and operand
188 /// nnnn is the ID of the current instruction (0-based). This table
190 /// 0xnn is the lowest possible opcode for the current instruction, used for
194 /// @param o - The output stream to which the instruction table should b
[all...] |
| /external/proguard/src/proguard/optimize/peephole/ |
| GotoCommonCodeReplacer.java | 27 import proguard.classfile.instruction.*;
28 import proguard.classfile.instruction.visitor.InstructionVisitor;
94 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}
99 // Check if the instruction is an unconditional goto instruction that
126 codeAttributeEditor.replaceInstruction( deleteOffset, (Instruction)null);
127 codeAttributeEditor.insertBeforeInstruction(deleteOffset, (Instruction)null);
128 codeAttributeEditor.insertAfterInstruction( deleteOffset, (Instruction)null);
134 // Redirect the goto instruction, if it is still necessary
[all...] |
| /external/llvm/lib/Transforms/Utils/ |
| BypassSlowDivision.cpp | 73 // insertFastDiv - Substitutes the div/rem instruction with code that checks the
74 // value of the operands and uses a shorter-faster div/rem instruction when
75 // possible and the longer-slower div/rem instruction otherwise.
83 // Get instruction operands
84 Instruction *Instr = J;
121 Value *ShortDivisorV = FastBuilder.CreateCast(Instruction::Trunc, Divisor,
123 Value *ShortDividendV = FastBuilder.CreateCast(Instruction::Trunc, Dividend,
131 Value *FastQuotientV = FastBuilder.CreateCast(Instruction::ZExt,
134 Value *FastRemainderV = FastBuilder.CreateCast(Instruction::ZExt,
170 // point iterator J at first instruction of successorB
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | 56 if (I->getOpcode() == Instruction::LShr && !I->isExact()) {
61 if (I->getOpcode() == Instruction::Shl && !I->hasNoUnsignedWrap()) {
117 Instruction *InstCombiner::visitMul(BinaryOperator &I) {
198 if (Instruction *R = FoldOpIntoSelect(I, SI))
202 if (Instruction *NV = FoldOpIntoPhi(I))
216 (BO->getOpcode() != Instruction::UDiv &&
217 BO->getOpcode() != Instruction::SDiv)) {
224 (BO->getOpcode() == Instruction::UDiv ||
225 BO->getOpcode() == Instruction::SDiv)) {
237 if (BO->getOpcode() == Instruction::UDiv
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| OutputCollector.java | 31 * {@code non-null;} the associated finisher (which holds the instruction
57 * Adds an instruction to the output.
59 * @param insn {@code non-null;} the instruction to add
68 * indicated instruction really is a reversible branch.
71 * {@code 0} is the most recently added instruction,
72 * {@code 1} is the instruction before that, etc.
80 * Adds an instruction to the output suffix.
82 * @param insn {@code non-null;} the instruction to add
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| OutputCollector.java | 32 * {@code non-null;} the associated finisher (which holds the instruction
59 * Adds an instruction to the output.
61 * @param insn {@code non-null;} the instruction to add
70 * indicated instruction really is a reversible branch.
73 * {@code 0} is the most recently added instruction,
74 * {@code 1} is the instruction before that, etc.
82 * Adds an instruction to the output suffix.
84 * @param insn {@code non-null;} the instruction to add
|
| /dalvik/vm/compiler/template/armv5te/ |
| TEMPLATE_MONITOR_ENTER_DEBUG.S | 9 * r4 - the Dalvik PC of the following instruction.
21 sub r0, r4, #2 @ roll dPC back to this monitor instruction
|
| /dalvik/vm/compiler/template/mips/ |
| TEMPLATE_MONITOR_ENTER_DEBUG.S | 9 * rPC - the Dalvik PC of the following instruction.
21 sub a0, rPC, 2 # roll dPC back to this monitor instruction
|
| funop.S | 4 * specifies an instruction that performs "result = op a0".
5 * This could be a MIPS instruction or a function call.
|
| /dalvik/vm/mterp/arm-vfp/ |
| fbinop2addr.S | 3 * an "instr" line that specifies an instruction that performs
21 GOTO_OPCODE(ip) @ jump to next instruction
|
| fbinopWide.S | 3 * Provide an "instr" line that specifies an instruction that performs
23 GOTO_OPCODE(ip) @ jump to next instruction
|
| fbinopWide2addr.S | 3 * an "instr" line that specifies an instruction that performs
22 GOTO_OPCODE(ip) @ jump to next instruction
|
| funop.S | 3 * line that specifies an instruction that performs "s1 = op s0".
18 GOTO_OPCODE(ip) @ jump to next instruction
|
| funopNarrower.S | 3 * "instr" line that specifies an instruction that performs "s0 = op d0".
18 GOTO_OPCODE(ip) @ jump to next instruction
|
| funopWider.S | 3 * "instr" line that specifies an instruction that performs "d0 = op s0".
18 GOTO_OPCODE(ip) @ jump to next instruction
|
| /dalvik/vm/mterp/armv5te/ |
| alt_stub.S | 2 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
3 * any interesting requests and then jump to the real instruction
|
| /dalvik/vm/mterp/armv6t2/ |
| unopWider.S | 4 * that specifies an instruction that performs "result = op r0", where
19 GOTO_OPCODE(ip) @ jump to next instruction
|
| /dalvik/vm/mterp/mips/ |
| alt_stub.S | 2 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
3 * any interesting requests and then jump to the real instruction
|
| unop.S | 4 * specifies an instruction that performs "result = op a0".
5 * This could be a MIPS instruction or a function call.
|
| unopWider.S | 4 * that specifies an instruction that performs "result = op a0", where
19 GOTO_OPCODE(t0) # jump to next instruction
|
| /dalvik/vm/mterp/x86/ |
| OP_MONITOR_EXIT.S | 8 * if they happened at the following instruction. See the Dalvik
9 * instruction spec.
|
| alt_stub.S | 2 * Inter-instruction transfer stub. Call out to dvmCheckBefore to handle
3 * any interesting requests and then jump to the real instruction
|
