| /external/v8/src/ |
| disassembler.h | 43 // instruction could be decoded.
49 // Decode instruction at pc and print disassembled instruction into f.
50 // Returns the instruction length in bytes, or 1 if the instruction could
|
| /external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
| OutputFinisher.java | 38 * Processor for instruction lists, which takes a "first cut" of
39 * instruction selection as a basis and produces a "final cut" in the
55 /** whether any instruction has position info */
58 /** whether any instruction has local variable info */
108 * instruction for local variable information.
110 * @param insn {@code non-null;} instruction to scrutinize
111 * @return {@code true} iff the instruction refers to any
164 * a single instruction.
167 * @param insn {@code non-null;} instruction to scrutinize
218 * Adds an instruction to the output
[all...] |
| /external/apache-xml/src/main/java/org/apache/xalan/templates/ |
| ElemPI.java | 31 * Implement xsl:processing-instruction.
33 * <!ELEMENT xsl:processing-instruction %char-template;>
34 * <!ATTLIST xsl:processing-instruction
47 * The xsl:processing-instruction element has a required name
48 * attribute that specifies the name of the processing instruction node.
115 * Create a processing instruction in the result tree.
116 * The content of the xsl:processing-instruction element is a
117 * template for the string-value of the processing instruction node.
134 // Ignore processing instruction if name is null
146 // Ignore processing instruction, if invali
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| PHITransAddr.h | 18 #include "llvm/IR/Instruction.h"
46 SmallVector<Instruction*, 4> InstInputs;
49 // If the address is an instruction, the whole thing is considered an input.
50 if (Instruction *I = dyn_cast<Instruction>(Addr))
88 SmallVectorImpl<Instruction*> &NewInsts);
107 SmallVectorImpl<Instruction*> &NewInsts);
109 /// AddAsInput - If the specified value is an instruction, add it as an input.
111 // If V is an instruction, it is now an input.
112 if (Instruction *VI = dyn_cast<Instruction>(V)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| DFAPacketizer.h | 16 // the packetizing mechanism, the input is the set of instruction classes for
19 // models the addition of an instruction to a packet. In the DFA constructed
20 // by this class, if an instruction can be added to a packet, then a valid
22 // indicate that the instruction cannot be added to the current packet.
75 // instruction are available in the current state.
79 // instruction and change the current state to reflect that change.
86 // packetizer works on machine basic blocks. For each instruction I in BB, the
88 // execute I. If so, the packetizer checks if I depends on any instruction J in
136 // an instruction. This function is supposed to be overrided by
146 // isSoloInstruction - return true if instruction MI can not be packetize
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZPatterns.td | 12 multiclass SXU<SDPatternOperator operator, Instruction insn> {
23 Instruction insn> {
32 Instruction insn> {
45 PatFrag imm, Instruction insn>
52 Instruction insn> {
59 multiclass InsertMem<string type, Instruction insn, RegisterOperand cls,
69 // Use MVC instruction INSN for a load of type LOAD followed by a store
73 ValueType vt, Instruction insn, bits<5> length> {
84 // registers in CLS against zero. The instruction has separate R1 and R2
85 // operands, but they must be the same when the instruction is used like this
[all...] |
| SystemZInstrInfo.h | 1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
66 // An instruction that branches on the current value of CC.
69 // An instruction that peforms a 32-bit signed comparison and branches
73 // An instruction that peforms a 64-bit signed comparison and branches
77 // An instruction that decrements a 32-bit register and branches if
81 // An instruction that decrements a 64-bit register and branches if
85 // Information about a branch instruction.
191 // values on which the instruction will branch, and set Target
200 // Opcode is the opcode of an instruction that has an address operand,
201 // and the caller wants to perform that instruction's operation on a
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| DCE.cpp | 22 #include "llvm/IR/Instruction.h"
45 Instruction *Inst = DI++;
63 "Dead Instruction Elimination", false, false)
95 std::vector<Instruction*> WorkList;
105 Instruction *I = WorkList.back();
108 if (isInstructionTriviallyDead(I, TLI)) { // If the instruction is dead.
109 // Loop over all of the values that the instruction uses, if there are
114 if (Instruction *Used = dyn_cast<Instruction>(*OI))
117 // Remove the instruction
[all...] |
| ADCE.cpp | 53 SmallPtrSet<Instruction*, 128> alive;
54 SmallVector<Instruction*, 128> worklist;
68 Instruction* curr = worklist.pop_back_val();
69 for (Instruction::op_iterator OI = curr->op_begin(), OE = curr->op_end();
71 if (Instruction* Inst = dyn_cast<Instruction>(OI))
86 for (SmallVectorImpl<Instruction *>::iterator I = worklist.begin(),
|
| /external/llvm/test/MC/ARM/ |
| diagnostics.s | 6 @ 's' bit on an instruction that can't accept it.
8 @ CHECK-ERRORS: error: instruction 'mls' can not set flags,
94 @ CHECK-ERRORS: error: invalid operand for instruction
104 @ CHECK-ERRORS: error: invalid operand for instruction
105 @ CHECK-ERRORS: error: invalid operand for instruction
106 @ CHECK-ERRORS: error: invalid operand for instruction
107 @ CHECK-ERRORS: error: invalid operand for instruction
125 @ CHECK-ERRORS: error: invalid operand for instruction
126 @ CHECK-ERRORS: error: invalid operand for instruction
127 @ CHECK-ERRORS: error: invalid operand for instruction
[all...] |
| /external/llvm/test/Transforms/LoopVectorize/ARM/ |
| mul-cast-vect.ll | 24 ; COST: cost of 2 for instruction: {{.*}} mul <4 x i32>
39 ; COST: cost of 0 for instruction: {{.*}} sext <4 x i16> {{.*}} to <4 x i32>
41 ; COST: cost of 2 for instruction: {{.*}} mul <4 x i32>
56 ; COST: cost of 0 for instruction: {{.*}} zext <4 x i16> {{.*}} to <4 x i32>
58 ; COST: cost of 2 for instruction: {{.*}} mul <4 x i32>
73 ; COST: cost of 1 for instruction: {{.*}} mul <2 x i32>
76 ; COST: cost of 1 for instruction: {{.*}} sext <2 x i32> {{.*}} to <2 x i64>
90 ; COST: cost of 1 for instruction: {{.*}} mul <2 x i32>
93 ; COST: cost of 1 for instruction: {{.*}} zext <2 x i32> {{.*}} to <2 x i64>
107 ; COST: cost of 2 for instruction: {{.*}} mul <4 x i32
[all...] |
| /external/chromium/sdch/open-vcdiff/src/ |
| decodetable.cc | 17 // as VCDIFF instruction types, based on a VCDiffCodeTableData structure.
65 // There is a second instruction left over
75 // Ran off end of instruction stream
81 // save a pointer to the second instruction, which should be returned
94 // Parse the size as a Varint in the instruction stream.
98 LOG(ERROR) << "Instruction size is not a valid variable-length integer"
102 UnGetInstruction(); // Rewind to instruction start
|
| /external/chromium_org/sandbox/win/src/sidestep/ |
| preamble_patcher.h | 16 // bytes + the max instruction size + 5 more bytes for our jump back to
41 // - If there is a jump (jxx) instruction in the first 5 bytes of
47 // - If there is a return (ret) instruction in the first 5 bytes
49 // for the jmp instruction we use to inject our patch.
55 // patcher at an invalid instruction (e.g. into the middle of a multi-
56 // byte instruction, or not at memory containing executable instructions)
58 // instruction boundaries.
|
| /external/chromium_org/sdch/open-vcdiff/src/ |
| decodetable.cc | 17 // as VCDIFF instruction types, based on a VCDiffCodeTableData structure.
65 // There is a second instruction left over
75 // Ran off end of instruction stream
81 // save a pointer to the second instruction, which should be returned
94 // Parse the size as a Varint in the instruction stream.
98 VCD_ERROR << "Instruction size is not a valid variable-length integer"
102 UnGetInstruction(); // Rewind to instruction start
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_build_util.cpp | 65 Instruction *
68 Instruction *insn = new_Instruction(func, op, ty);
77 Instruction *
81 Instruction *insn = new_Instruction(func, op, ty);
91 Instruction *
95 Instruction *insn = new_Instruction(func, op, ty);
109 Instruction *insn = new_Instruction(func, OP_LOAD, ty);
121 Instruction *
125 Instruction *insn = new_Instruction(func, op, ty);
136 Instruction *
[all...] |
| /external/llvm/docs/HistoricalNotes/ |
| 2000-11-18-EarlyDesignIdeas.txt | 41 -- an instruction to say "I speculate that these two values are not
44 -- or an instruction to check whether two values are aliased and
49 A "thread-id" field on every instruction that allows the static
52 This has very powerful uses, but thread-id on every instruction
53 is expensive in terms of instruction size and code size.
61 o Or forget all this and stick to a traditional instruction set?
65 that you had suggested doing instruction scheduling on SSA form instead
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.h | 1 //===-- SparcInstrInfo.h - Sparc Instruction Information --------*- C++ -*-===//
26 /// instruction info tracks.
44 /// such, whenever a client has an instance of instruction info, it should
49 /// isLoadFromStackSlot - If the specified machine instruction is a direct
52 /// not, return 0. This predicate must return 0 if the instruction has
57 /// isStoreToStackSlot - If the specified machine instruction is a direct
60 /// not, return 0. This predicate must return 0 if the instruction has
|
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_build_util.cpp | 65 Instruction *
68 Instruction *insn = new_Instruction(func, op, ty);
77 Instruction *
81 Instruction *insn = new_Instruction(func, op, ty);
91 Instruction *
95 Instruction *insn = new_Instruction(func, op, ty);
109 Instruction *insn = new_Instruction(func, OP_LOAD, ty);
121 Instruction *
125 Instruction *insn = new_Instruction(func, op, ty);
136 Instruction *
[all...] |
| /external/open-vcdiff/src/ |
| decodetable.cc | 17 // as VCDIFF instruction types, based on a VCDiffCodeTableData structure.
65 // There is a second instruction left over
75 // Ran off end of instruction stream
81 // save a pointer to the second instruction, which should be returned
94 // Parse the size as a Varint in the instruction stream.
98 VCD_ERROR << "Instruction size is not a valid variable-length integer"
102 UnGetInstruction(); // Rewind to instruction start
|
| /external/proguard/src/proguard/optimize/info/ |
| SideEffectMethodMarker.java | 26 import proguard.classfile.instruction.*;
137 // Get the current instruction.
138 Instruction instruction = InstructionFactory.create(code, offset); local
145 instruction))
150 // Go to the next instruction.
151 offset += instruction.length(offset);
|
| /external/proguard/src/proguard/optimize/peephole/ |
| UnreachableExceptionRemover.java | 26 import proguard.classfile.instruction.*;
122 // Get the current instruction.
123 Instruction instruction = InstructionFactory.create(code, offset); local
130 instruction))
135 // Go to the next instruction.
136 offset += instruction.length(offset);
|
| /external/proguard/src/proguard/classfile/editor/ |
| CodeAttributeComposer.java | 28 import proguard.classfile.instruction.*;
29 import proguard.classfile.instruction.visitor.InstructionVisitor;
161 * Appends the given instruction with the given old offset.
162 * @param oldInstructionOffset the old offset of the instruction, to which
165 * @param instruction the instruction to be appended.
168 Instruction instruction)
172 println("["+codeLength+"] <- ", instruction.toString(oldInstructionOffset));
176 int newCodeLength = codeLength + instruction.length(codeLength)
276 Instruction instruction = InstructionFactory.create(code, instructionOffset); local
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetItinerary.td | 11 // which should be implemented by each target that uses instruction
13 // tables for each instruction class. They are most appropriate for
23 // during scheduling and has an affect instruction order based on availability
43 // Instruction stage - These values represent a non-pipelined step in
44 // the execution of an instruction. Cycles represents the number of
67 // Instruction itinerary - An itinerary represents a sequential series of steps
68 // required to complete an instruction. Itineraries are represented as lists of
69 // instruction stages.
73 // Instruction itinerary classes - These values represent 'named' instruction
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600InstrInfo.h | 1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
64 /// \returns true if this \p Opcode represents an ALU instruction.
83 /// of the instruction's src operands.
108 /// starting from the one already provided in the Instruction Group MIs that
113 /// apply to the last instruction.
114 /// PV holds GPR to PV registers in the Instruction Group MIs.
120 /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
128 /// instruction slots within an instruction group.
219 /// all the instruction modifiers initialized to their default values
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenInstruction.h | 1 //===- CodeGenInstruction.h - Instruction Class Wrapper ---------*- C++ -*-===//
10 // This file defines a wrapper class for the 'Instruction' TableGen class.
63 /// operand list for a tablegen instruction.
131 /// elements in the instruction's (outs) list.
154 /// non-empty name. If the instruction does not have an operand with the
158 /// hasOperandNamed - Query whether the instruction has an operand of the
202 Record *TheDef; // The actual record defining this instruction.
203 std::string Namespace; // The namespace the instruction is in.
206 /// instruction.
210 /// to the instruction
[all...] |
