| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_lowering_nvc0.cpp | 49 void handleDIV(Instruction *); // integer division, modulus
50 void handleRCPRSQ(Instruction *); // double precision float recip/rsqrt
57 NVC0LegalizeSSA::handleDIV(Instruction *i)
84 NVC0LegalizeSSA::handleRCPRSQ(Instruction *i)
99 Instruction *next;
100 for (Instruction *i = bb->getEntry(); i; i = next) {
130 void replaceZero(Instruction *);
131 void split64BitOp(Instruction *);
137 TexUse(Instruction *use, const Instruction *tex
[all...] |
| nv50_ir_emit_nvc0.cpp | 34 virtual bool emitInstruction(Instruction *);
35 virtual uint32_t getMinEncodingSize(const Instruction *) const;
48 void emitForm_A(const Instruction *, uint64_t);
49 void emitForm_B(const Instruction *, uint64_t);
50 void emitForm_S(const Instruction *, uint32_t, bool pred);
52 void emitPredicate(const Instruction *);
55 void setImmediate(const Instruction *, const int s); // needs op already set
59 void emitInterpMode(const Instruction *);
67 void roundMode_A(const Instruction *);
68 void roundMode_C(const Instruction *);
[all...] |
| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_lowering_nvc0.cpp | 49 void handleDIV(Instruction *); // integer division, modulus
50 void handleRCPRSQ(Instruction *); // double precision float recip/rsqrt
57 NVC0LegalizeSSA::handleDIV(Instruction *i)
84 NVC0LegalizeSSA::handleRCPRSQ(Instruction *i)
99 Instruction *next;
100 for (Instruction *i = bb->getEntry(); i; i = next) {
130 void replaceZero(Instruction *);
131 void split64BitOp(Instruction *);
137 TexUse(Instruction *use, const Instruction *tex
[all...] |
| nv50_ir_emit_nvc0.cpp | 34 virtual bool emitInstruction(Instruction *);
35 virtual uint32_t getMinEncodingSize(const Instruction *) const;
48 void emitForm_A(const Instruction *, uint64_t);
49 void emitForm_B(const Instruction *, uint64_t);
50 void emitForm_S(const Instruction *, uint32_t, bool pred);
52 void emitPredicate(const Instruction *);
55 void setImmediate(const Instruction *, const int s); // needs op already set
59 void emitInterpMode(const Instruction *);
67 void roundMode_A(const Instruction *);
68 void roundMode_C(const Instruction *);
[all...] |
| /external/llvm/lib/Target/CppBackend/ |
| CPPBackend.cpp | 23 #include "llvm/IR/Instruction.h"
158 void printInstruction(const Instruction *I, const std::string& bbname);
815 if (CE->getOpcode() == Instruction::GetElementPtr) {
834 case Instruction::Trunc: Out << "Instruction::Trunc"; break;
835 case Instruction::ZExt: Out << "Instruction::ZExt"; break;
836 case Instruction::SExt: Out << "Instruction::SExt"; break;
837 case Instruction::FPTrunc: Out << "Instruction::FPTrunc"; break
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| FastISel.h | 28 class Instruction;
45 /// This is a fast-path instruction selection class that generates poor code and
62 /// The position of the last instruction for materializing constants for use
68 /// The top most instruction in the current block that is allowed for emitting
74 /// Return the position of the last instruction emitted for materializing
78 /// Update the position of the last instruction emitted for materializing
92 /// Do "fast" instruction selection for function arguments and append machine
96 /// Do "fast" instruction selection for the given LLVM IR instruction, and
99 bool SelectInstruction(const Instruction *I)
[all...] |
| /external/llvm/lib/MC/ |
| MCStreamer.cpp | 262 MCCFIInstruction Instruction =
265 CurFrame->Instructions.push_back(Instruction);
270 MCCFIInstruction Instruction =
273 CurFrame->Instructions.push_back(Instruction);
278 MCCFIInstruction Instruction =
281 CurFrame->Instructions.push_back(Instruction);
286 MCCFIInstruction Instruction =
289 CurFrame->Instructions.push_back(Instruction);
294 MCCFIInstruction Instruction =
297 CurFrame->Instructions.push_back(Instruction);
[all...] |
| /external/v8/src/mips/ |
| simulator-mips.h | 185 // instruction.
251 void Format(Instruction* instr, const char* format);
259 inline uint16_t ReadHU(int32_t addr, Instruction* instr);
260 inline int16_t ReadH(int32_t addr, Instruction* instr);
262 inline void WriteH(int32_t addr, uint16_t value, Instruction* instr);
263 inline void WriteH(int32_t addr, int16_t value, Instruction* instr);
265 inline int ReadW(int32_t addr, Instruction* instr);
266 inline void WriteW(int32_t addr, int value, Instruction* instr);
268 inline double ReadD(int32_t addr, Instruction* instr);
269 inline void WriteD(int32_t addr, double value, Instruction* instr)
[all...] |
| /external/llvm/docs/ |
| HowToUseInstrMappings.rst | 2 How To Use Instruction Mappings
11 This document contains information about adding instruction mapping support
13 between different instruction formats during various optimizations. One approach
16 because of the hardcoded instruction names. Also, whenever a new instruction is
50 // the key instruction. This is the instruction that will be transformed
56 // instruction will be transformed into.
65 takes a non-predicated instruction and returns its predicated true or false form
70 instruction since they are the one used to query the interface function
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| ScalarEvolutionExpander.h | 44 std::map<std::pair<const SCEV *, Instruction *>, TrackingVH<Value> >
55 /// returns the add instruction that adds one to the phi for {0,+,1}<L>,
67 Instruction *IVIncInsertPos;
124 Instruction *getIVIncOperand(Instruction *IncV, Instruction *InsertPos,
128 bool hoistIVInc(Instruction *IncV, Instruction *InsertPos);
139 Value *expandCodeFor(const SCEV *SH, Type *Ty, Instruction *I);
142 void setIVIncInsertPos(const Loop *L, Instruction *Pos)
[all...] |
| /dalvik/dx/src/com/android/dx/ssa/ |
| LiteralOpUpgrader.java | 109 * An if instruction can become an if-*z instruction.
125 * An instruction can be commuted to a literal operation
139 * Tries to replace an instruction with a const instruction. The given
140 * instruction must have a constant result for it to be replaced.
142 * @param insn {@code non-null;} instruction to try to replace
143 * @return true if the instruction was replaced
154 // Replace the instruction with a constant
183 * @param cst {@code null-ok;} constant for new instruction, if an
[all...] |
| /dalvik/libdex/ |
| InstrUtils.h | 18 * Dalvik instruction utility functions.
27 * Possible instruction formats associated with Dalvik opcodes.
30 * opcodes and instruction formats.
84 * Instruction width implied by an opcode's format; a value in the
127 * Holds the contents of a decoded instruction.
140 * Return the instruction width of the specified opcode, or 0 if not defined.
149 * Return the width of the specified instruction, or 0 if not defined. Also
173 * Return the instruction format for the specified opcode.
182 * Return the instruction index type for the specified opcode.
191 * Decode the instruction pointed to by "insns"
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_program.h | 73 * This instruction format is intended to be expanded for hardware-specific
75 * instruction types may be valid.
82 * Opcode of this instruction, according to \ref rc_opcode enums.
110 /** True if tex instruction should do shadow comparison */
122 * this instruction. */
153 * Instructions.Next points to the first instruction,
154 * Instructions.Prev points to the last instruction.
171 * The function will be called once for each instruction.
172 * It has to either emit the appropriate transformed code for the instruction
174 * instruction
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/ssa/ |
| LiteralOpUpgrader.java | 110 * An if instruction can become an if-*z instruction.
126 * An instruction can be commuted to a literal operation
140 * Tries to replace an instruction with a const instruction. The given
141 * instruction must have a constant result for it to be replaced.
143 * @param insn {@code non-null;} instruction to try to replace
144 * @return true if the instruction was replaced
155 // Replace the instruction with a constant
184 * @param cst {@code null-ok;} constant for new instruction, if an
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCDisassembler.h | 31 /// Success, however some have a concept of an instruction with
66 /// getInstruction - Returns the disassembly of a single instruction.
69 /// instruction.
70 /// @param size - A value to populate with the size of the instruction, or
72 /// an invalid instruction.
75 /// byte of the instruction.
78 /// @return - MCDisassembler::Success if the instruction is valid,
79 /// MCDisassembler::SoftFail if the instruction was
81 /// MCDisassembler::Fail if the instruction was invalid.
103 // Subtarget information, for instruction decoding predicates if required
[all...] |
| /external/llvm/lib/Transforms/Utils/ |
| DemoteRegToStack.cpp | 20 /// Instruction and replaces it with a slot in the stack frame, allocated via
24 AllocaInst *llvm::DemoteRegToStack(Instruction &I, bool VolatileLoads,
25 Instruction *AllocaPoint) {
42 // Change all of the users of the instruction to read from the stack slot.
44 Instruction *U = cast<Instruction>(I.use_back());
68 // If this is a normal instruction, just insert a load.
76 // careful if I is an invoke instruction, because we can't insert the store
77 // AFTER the terminator instruction.
110 AllocaInst *llvm::DemotePHIToStack(PHINode *P, Instruction *AllocaPoint)
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_program.h | 73 * This instruction format is intended to be expanded for hardware-specific
75 * instruction types may be valid.
82 * Opcode of this instruction, according to \ref rc_opcode enums.
110 /** True if tex instruction should do shadow comparison */
122 * this instruction. */
153 * Instructions.Next points to the first instruction,
154 * Instructions.Prev points to the last instruction.
171 * The function will be called once for each instruction.
172 * It has to either emit the appropriate transformed code for the instruction
174 * instruction
[all...] |
| /external/valgrind/main/docs/internals/ |
| arm_thumb_notes_gdbserver.txt | 9 not equal to the address of the instruction being executed: the fact
10 that the instruction being executed is a thumb instruction is
30 When instrumenting a SB for gdbserver, a PUT of the current instruction
34 to guess the next program counter after this instruction.
38 of the instruction being instrumented, the thumb bit must be accessible
44 When a breakpoint is placed at an instruction, the translation for this
45 instruction must be discarded to have the SB re-instrumented for gdbserver.
50 fact that the instruction is a thumb instruction
[all...] |
| /external/llvm/lib/Analysis/ |
| CaptureTracking.cpp | 103 Instruction *I = cast<Instruction>(U->getUser());
107 case Instruction::Call:
108 case Instruction::Invoke: {
131 case Instruction::Load:
134 case Instruction::VAArg:
137 case Instruction::Store:
144 case Instruction::BitCast:
145 case Instruction::GetElementPtr:
146 case Instruction::PHI
[all...] |
| /external/smali/dexlib/src/main/java/org/jf/dexlib/Code/Analysis/ |
| InlineMethodResolver.java | 52 public abstract DeodexUtil.InlineMethod resolveExecuteInline(AnalyzedInstruction instruction);
79 assert analyzedInstruction.instruction instanceof OdexedInvokeInline;
81 OdexedInvokeInline instruction = (OdexedInvokeInline)analyzedInstruction.instruction; local
82 int inlineIndex = instruction.getInlineIndex();
151 assert analyzedInstruction.instruction instanceof OdexedInvokeInline;
153 OdexedInvokeInline instruction = (OdexedInvokeInline)analyzedInstruction.instruction; local
154 int inlineIndex = instruction.getInlineIndex();
161 int parameterCount = getParameterCount(instruction);
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCasts.cpp | 44 if (I->getOpcode() == Instruction::Shl) {
51 if (I->getOpcode() == Instruction::Mul) {
58 if (I->getOpcode() == Instruction::Add) {
77 /// PromoteCastOfAllocation - If we find a cast of an allocation instruction,
79 Instruction *InstCombiner::PromoteCastOfAllocation(BitCastInst &CI,
149 // New is the allocation instruction, pointer typed. AI is the original
150 // allocation instruction, also pointer typed. Thus, cast to use is BitCast.
170 // Otherwise, it must be an instruction.
171 Instruction *I = cast<Instruction>(V)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_lowering_nv50.cpp | 41 expandIntegerMUL(BuildUtil *bld, Instruction *mul)
58 Instruction *i[9];
124 void replaceZero(Instruction *);
125 void split64BitOp(Instruction *);
139 std::list<Instruction *> *outWrites =
140 reinterpret_cast<std::list<Instruction *> *>(prog->targetPriv);
143 for (std::list<Instruction *>::iterator it = outWrites->begin();
154 NV50LegalizePostRA::replaceZero(Instruction *i)
164 NV50LegalizePostRA::split64BitOp(Instruction *i)
206 Instruction *skip = new_FlowInstruction(func, OP_PRERET, bbT)
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_lowering_nv50.cpp | 41 expandIntegerMUL(BuildUtil *bld, Instruction *mul)
58 Instruction *i[9];
124 void replaceZero(Instruction *);
125 void split64BitOp(Instruction *);
139 std::list<Instruction *> *outWrites =
140 reinterpret_cast<std::list<Instruction *> *>(prog->targetPriv);
143 for (std::list<Instruction *>::iterator it = outWrites->begin();
154 NV50LegalizePostRA::replaceZero(Instruction *i)
164 NV50LegalizePostRA::split64BitOp(Instruction *i)
206 Instruction *skip = new_FlowInstruction(func, OP_PRERET, bbT)
[all...] |
| /external/chromium_org/v8/src/mips/ |
| simulator-mips.h | 185 // instruction.
255 void Format(Instruction* instr, const char* format);
263 inline uint16_t ReadHU(int32_t addr, Instruction* instr);
264 inline int16_t ReadH(int32_t addr, Instruction* instr);
266 inline void WriteH(int32_t addr, uint16_t value, Instruction* instr);
267 inline void WriteH(int32_t addr, int16_t value, Instruction* instr);
269 inline int ReadW(int32_t addr, Instruction* instr);
270 inline void WriteW(int32_t addr, int value, Instruction* instr);
272 inline double ReadD(int32_t addr, Instruction* instr);
273 inline void WriteD(int32_t addr, double value, Instruction* instr)
[all...] |
| /art/runtime/ |
| disassembler_mips.cc | 34 bool Matches(uint32_t instruction) const {
35 return (instruction & mask) == value;
172 uint32_t instruction = ReadU32(instr_ptr); local
174 uint32_t rs = (instruction >> 21) & 0x1f; // I-type, R-type.
175 uint32_t rt = (instruction >> 16) & 0x1f; // I-type, R-type.
176 uint32_t rd = (instruction >> 11) & 0x1f; // R-type.
177 uint32_t sa = (instruction >> 6) & 0x1f; // R-type.
183 uint32_t op = (instruction >> 26) & 0x3f;
184 uint32_t function = (instruction & 0x3f); // R-type.
188 if (gMipsInstructions[i].Matches(instruction)) {
[all...] |
