| /external/llvm/lib/Transforms/Vectorize/ |
| BBVectorize.cpp | 68 cl::desc("The maximum search distance for instruction pairs"));
92 cl::desc("The maximum number of candidate instruction pairs per group"));
155 cl::desc("Use a fast instruction dependency analysis"));
159 DebugInstructionExamination("bb-vectorize-debug-instruction-examination",
162 " instruction-examination process"));
272 bool isInstVectorizable(Instruction *I, bool &IsSimpleLoadStore);
274 bool areInstsCompatible(Instruction *I, Instruction *J,
279 AliasSetTracker &WriteSet, Instruction *I,
280 Instruction *J, bool UpdateUsers = true
[all...] |
| LoopVectorize.cpp | 163 // Widen each instruction in the old loop to a new one in the new loop.
175 /// originated from one scalar instruction.
185 Instruction *addRuntimeCheck(LoopVectorizationLegality *Legal,
186 Instruction *Loc);
208 /// This instruction is un-vectorizable. Implement it as a sequence
210 void scalarizeInstruction(Instruction *Instr);
213 void vectorizeMemoryInstruction(Instruction *Instr,
216 /// Create a broadcast instruction. This method generates a broadcast
217 /// instruction (shuffle) for loop invariant values and for the induction
329 /// \brief Look for a meaningful debug location on the instruction or it'
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_pair_schedule.c | 45 struct rc_instruction * Instruction;
47 /** Next instruction in the linked list of ready instructions. */
50 /** Values that this instruction reads and writes */
58 * this instruction can be scheduled.
63 * "all readers"), even those outside the basic block this instruction
67 /** If the scheduler has paired an RGB and an Alpha instruction together,
73 * instruction to schedule. Instructions with a higher value of Score
77 /** The number of components that read from a TEX instruction. */
111 * of the instruction writing \ref Next is decremented.
190 fprintf(stderr,"%u (%d) [%u],", ptr->Instruction->IP, score
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineSelect.cpp | 80 /// Assuming that the specified instruction is an operand to the select, return
81 /// a bitmask indicating which operands of this instruction are foldable if they
84 static unsigned GetSelectFoldableOperands(Instruction *I) {
86 case Instruction::Add:
87 case Instruction::Mul:
88 case Instruction::And:
89 case Instruction::Or:
90 case Instruction::Xor:
92 case Instruction::Sub: // Can only fold on the amount subtracted.
93 case Instruction::Shl: // Can only fold on the shift amount
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_pair_schedule.c | 45 struct rc_instruction * Instruction;
47 /** Next instruction in the linked list of ready instructions. */
50 /** Values that this instruction reads and writes */
58 * this instruction can be scheduled.
63 * "all readers"), even those outside the basic block this instruction
67 /** If the scheduler has paired an RGB and an Alpha instruction together,
73 * instruction to schedule. Instructions with a higher value of Score
77 /** The number of components that read from a TEX instruction. */
111 * of the instruction writing \ref Next is decremented.
190 fprintf(stderr,"%u (%d) [%u],", ptr->Instruction->IP, score
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| TargetInsn.java | 23 * Instruction which has a single branch target.
81 * Gets the unique branch target of this instruction.
90 * Gets the target address of this instruction. This is only valid
91 * to call if the target instruction has been assigned an address,
102 * Gets the branch offset of this instruction. This is only valid to
103 * call if both this and the target instruction each has been assigned
|
| /dalvik/dexgen/src/com/android/dexgen/rop/code/ |
| InsnList.java | 48 * Sets the instruction at the given index.
51 * @param insn {@code non-null;} the instruction to set at {@code n}
58 * Gets the last instruction. This is just a convenient shorthand for
61 * @return {@code non-null;} the last instruction
68 * Visits each instruction in the list, in order.
106 * the registers in each instruction are offset by the given
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| TargetInsn.java | 23 * Instruction which has a single branch target.
81 * Gets the unique branch target of this instruction.
90 * Gets the target address of this instruction. This is only valid
91 * to call if the target instruction has been assigned an address,
102 * Gets the branch offset of this instruction. This is only valid to
103 * call if both this and the target instruction each has been assigned
|
| InsnFormat.java | 32 * Base class for all instruction format handlers. Instruction format
47 * dump, of the given instruction. The instruction must be of this
50 * @param insn {@code non-null;} the instruction
77 * Returns the string form of the arguments to the given instruction.
78 * The instruction must be of this instance's format. If the instruction
84 * @param insn {@code non-null;} the instruction
90 * Returns the associated comment for the given instruction, if any
[all...] |
| /dalvik/dx/src/com/android/dx/rop/code/ |
| InsnList.java | 48 * Sets the instruction at the given index.
51 * @param insn {@code non-null;} the instruction to set at {@code n}
58 * Gets the last instruction. This is just a convenient shorthand for
61 * @return {@code non-null;} the last instruction
68 * Visits each instruction in the list, in order.
106 * the registers in each instruction are offset by the given
|
| /dalvik/opcode-gen/ |
| README.txt | 16 Notes on updating the sets of defined opcodes and instruction formats
33 * Implement/update the instruction in assembly in vm/mterp/{arm*,x86*}/...
34 * Verify by enabling the assembly (e.g. ARM) handler for that instruction
37 * Implement/update the instruction in
51 If you want to add, delete, or change instruction formats:
57 * Update the instruction format list in libdex/InstrUtils.h.
|
| /external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
| TargetInsn.java | 23 * Instruction which has a single branch target.
81 * Gets the unique branch target of this instruction.
90 * Gets the target address of this instruction. This is only valid
91 * to call if the target instruction has been assigned an address,
102 * Gets the branch offset of this instruction. This is only valid to
103 * call if both this and the target instruction each has been assigned
|
| /external/dexmaker/src/dx/java/com/android/dx/rop/code/ |
| InsnList.java | 48 * Sets the instruction at the given index.
51 * @param insn {@code non-null;} the instruction to set at {@code n}
58 * Gets the last instruction. This is just a convenient shorthand for
61 * @return {@code non-null;} the last instruction
68 * Visits each instruction in the list, in order.
106 * the registers in each instruction are offset by the given
|
| /external/dropbear/ |
| cli-authinteract.c | 70 unsigned char *instruction = NULL; local
83 instruction = buf_getstring(ses.payload, NULL);
105 if (strlen(instruction) > 0) {
106 cleantext(instruction);
107 fprintf(stderr, "%s", instruction);
109 m_free(instruction);
|
| /external/llvm/include/llvm/CodeGen/ |
| LiveVariables.h | 11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
14 // the instruction, but are never used after the instruction (i.e., they are
55 /// information: the set of blocks in which the instruction is live
56 /// throughout, the set of blocks in which the instruction is actually used,
60 /// There is one killing instruction, and AliveBlocks is empty.
67 /// lives until the specified instruction. Note that there cannot ever be a
92 /// machine instruction. Returns true if there was a kil
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCInstrInfo.h | 1 //===-- llvm/MC/MCInstrInfo.h - Target Instruction Info ---------*- C++ -*-===//
10 // This file describes the target machine instruction set.
24 /// MCInstrInfo - Interface to description of machine instruction set
29 const char *InstrNameData; // Instruction name string pool
45 /// get - Return the machine instruction descriptor that corresponds to the
46 /// specified instruction opcode.
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXSplitBBatBar.cpp | 9 // Split basic blocks so that a basic block that contains a barrier instruction
10 // only contains the barrier instruction.
30 SmallVector<Instruction *, 4> SplitPoints;
44 // If this is a barrier, split at this instruction
45 // and the next instruction.
63 Instruction *inst = SplitPoints[i];
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.h | 1 //===-- XCoreInstrInfo.h - XCore Instruction Information --------*- C++ -*-===//
31 /// such, whenever a client has an instance of instruction info, it should
36 /// isLoadFromStackSlot - If the specified machine instruction is a direct
39 /// not, return 0. This predicate must return 0 if the instruction has
44 /// isStoreToStackSlot - If the specified machine instruction is a direct
47 /// not, return 0. This predicate must return 0 if the instruction has
|
| /external/llvm/lib/Transforms/Scalar/ |
| ConstantProp.cpp | 27 #include "llvm/IR/Instruction.h"
65 std::set<Instruction*> WorkList;
74 Instruction *I = *WorkList.begin();
79 // Add all of the users of this instruction to the worklist, they might
83 WorkList.insert(cast<Instruction>(*UI));
88 // Remove the dead instruction.
|
| Reassociate.cpp | 64 static void PrintOps(Instruction *I, const SmallVectorImpl<ValueEntry> &Ops) {
66 dbgs() << Instruction::getOpcodeName(I->getOpcode()) << " "
163 SetVector<AssertingVH<Instruction> > RedoInsts;
183 Value *OptimizeAdd(Instruction *I, SmallVectorImpl<ValueEntry> &Ops);
184 Value *OptimizeXor(Instruction *I, SmallVectorImpl<ValueEntry> &Ops);
185 bool CombineXorOpnd(Instruction *I, XorOpnd *Opnd1, APInt &ConstOpnd,
187 bool CombineXorOpnd(Instruction *I, XorOpnd *Opnd1, XorOpnd *Opnd2,
195 void EraseInst(Instruction *I);
196 void OptimizeInst(Instruction *I);
203 Instruction *I = dyn_cast<Instruction>(V)
[all...] |
| /external/smali/dexlib/src/main/java/org/jf/dexlib/Code/Format/ |
| Instruction21c.java | 31 import org.jf.dexlib.Code.Instruction;
42 public static final Instruction.InstructionFactory Factory = new Factory();
77 throw new RuntimeException(String.format("%s index is too large. Use the %s instruction instead.",
97 public Instruction makeJumbo() {
110 private static class Factory implements Instruction.InstructionFactory {
111 public Instruction makeInstruction(DexFile dexFile, Opcode opcode, byte[] buffer, int bufferIndex) {
|
| Instruction22c.java | 31 import org.jf.dexlib.Code.Instruction;
42 public static final Instruction.InstructionFactory Factory = new Factory();
68 throw new RuntimeException(String.format("%s index is too large. Use the %s instruction instead.",
92 public Instruction makeJumbo() {
101 private static class Factory implements Instruction.InstructionFactory {
102 public Instruction makeInstruction(DexFile dexFile, Opcode opcode, byte[] buffer, int bufferIndex) {
|
| /external/llvm/include/llvm/Support/ |
| PatternMatch.h | 24 // This is primarily useful to things like the instruction combiner, but can
394 inline BinaryOp_match<LHS, RHS, Instruction::Add>
396 return BinaryOp_match<LHS, RHS, Instruction::Add>(L, R);
400 inline BinaryOp_match<LHS, RHS, Instruction::FAdd>
402 return BinaryOp_match<LHS, RHS, Instruction::FAdd>(L, R);
406 inline BinaryOp_match<LHS, RHS, Instruction::Sub>
408 return BinaryOp_match<LHS, RHS, Instruction::Sub>(L, R);
412 inline BinaryOp_match<LHS, RHS, Instruction::FSub>
414 return BinaryOp_match<LHS, RHS, Instruction::FSub>(L, R);
418 inline BinaryOp_match<LHS, RHS, Instruction::Mul
[all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.c | 11 * It contains the implementation of the instruction decoder.
38 * contextForAttrs - Client for the instruction context table. Takes a set of
43 * an instruction with these attributes.
50 * modRMRequired - Reads the appropriate instruction table to determine whether
51 * the ModR/M byte is required to decode a particular instruction.
54 * @param insnContext - The context for the instruction, as returned by
56 * @param opcode - The last byte of the instruction's opcode, not counting
91 * decode - Reads the appropriate instruction table to obtain the unique ID of
92 * an instruction.
98 * @return - The UID of the instruction, or 0 on failure
[all...] |
| /external/chromium_org/v8/src/arm/ |
| disasm-arm.cc | 28 // A Disassembler object is used to disassemble a block of code instruction by
29 // instruction. The default implementation of the NameConverter object can be
85 // Writes one disassembled instruction into 'buffer' (0-terminated).
86 // Returns the length of the disassembled machine instruction in bytes.
87 int InstructionDecode(byte* instruction);
101 int FormatVFPRegister(Instruction* instr, const char* format);
102 void PrintMovwMovt(Instruction* instr);
103 int FormatVFPinstruction(Instruction* instr, const char* format);
104 void PrintCondition(Instruction* instr);
105 void PrintShiftRm(Instruction* instr)
[all...] |
